DS50EV401_15 Datasheet, PDF (2/19 Pages) Texas Instruments – DS50EV401 2.5 Gbps / 5.0 Gbps or 8.0 Gbps Quad Cable and Backplane Equalizer

DS50EV401
SNLS288E – JANUARY 2008 – REVISED MARCH 2013
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PIN DESCRIPTIONS
Pin Name Pin Number I/O, Type
Description
HIGH SPEED DIFFERENTIAL I/O
IN_0+
IN_0-
1
I, CML Inverting and non-inverting CML differential inputs to the equalizer. An on-chip 50Ω
2
terminating resistor connects IN_0+ to VDD and IN_0- to VDD.
IN_1+
IN_1-
4
I, CML Inverting and non-inverting CML differential inputs to the equalizer. An on-chip 50Ω
5
terminating resistor connects IN_1+ to VDD and IN_1- to VDD.
IN_2+
IN_2-
8
I, CML Inverting and non-inverting CML differential inputs to the equalizer. An on-chip 50Ω
9
terminating resistor connects IN_2+ to VDD and IN_2- to VDD.
IN_3+
IN_3-
11
I, CML Inverting and non-inverting CML differential inputs to the equalizer. An on-chip 50Ω
12
terminating resistor connects IN_3+ to VDD and IN_3- to VDD.
OUT_0+
36
OUT_0-
35
OUT_1+
33
OUT_1-
32
OUT_2+
29
OUT_2-
28
OUT_3+
26
OUT_3-
25
EQUALIZATION CONTROL
O, CML
O, CML
O, CML
O, CML
Inverting and non-inverting CML differential outputs from the equalizer. An on-chip 50Ω
terminating resistor connects OUT_0+ to V_DD and OUT_0- to V_DD.
Inverting and non-inverting CML differential outputs from the equalizer. An on-chip 50Ω
terminating resistor connects OUT_1+ to V_DD and OUT_1- to V_DD.
Inverting and non-inverting CML differential outputs from the equalizer. An on-chip 50Ω
terminating resistor connects OUT_2+ to V_DD and OUT_2- to V_DD.
Inverting and non-inverting CML differential outputs from the equalizer. An on-chip 50Ω
terminating resistor connects OUT_3+ to V_DD and OUT_3- to V_DD.
MODE
14
I, LVCMOS MODE selects the equalizer frequency for EQ channels. MODE is internally pulled low.
L = 6.0 - 8.0 Gbps setting
H = 2.5 Gbps / 5.0 Gbps setting
DEVICE CONTROL
EN0
44
I, LVCMOS Channel 0 Enable Input Pin
H = normal operation (enabled)
L = standby mode
Pin is internally pulled High.
EN1
42
I, LVCMOS Channel 1 Enable Input Pin
H = normal operation (enabled)
L = standby mode
Pin is internally pulled High.
EN2
40
I, LVCMOS Channel 2 Enable Input Pin
H = normal operation (enabled)
L = standby mode
Pin is internally pulled High.
EN3
38
I, LVCMOS Channel 3 Enable Input Pin
H = normal operation (enabled)
L = standby mode
Pin is internally pulled High.
SD0
45
O, LVCMOS Channel 0 Signal Detect Output Pin
H = signal detected
L = no signal detected
SD1
43
O, LVCMOS Channel 1 Signal Detect Output Pin
H = signal detected
L = no signal detected
SD2
41
O, LVCMOS Channel 2 Signal Detect Output Pin
H = signal detected
L = no signal detected.
SD3
39
O, LVCMOS Channel 3 Signal Detect Output Pin
H = signal detected
L = no signal detected
POWER
V_DD
3, 6, 7,
Power V_DD = 2.5V ± 5% or 3.3V ± 10%. V_DD pins should be tied to V_DD plane through low
10, 13,
inductance path. A 0.1μF bypass capacitor should be connected between each V_DD pin to
15, 46
GND planes.
GND
22, 24,
27, 30,
31, 34
Ground
Ground reference. GND should be tied to a solid ground plane through a low impedance
path.
Exposed Pad
DAP
Ground
Ground reference. The exposed pad at the center of the package must be connected to
ground plane of the board.
2
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