DS50EV401_15 Datasheet, PDF (6/19 Pages) Texas Instruments – DS50EV401 2.5 Gbps / 5.0 Gbps or 8.0 Gbps Quad Cable and Backplane Equalizer

DS50EV401
SNLS288E – JANUARY 2008 – REVISED MARCH 2013
TIMING DIAGRAMS
Signal Source
A
6 mil FR4 Test Channel
SMA
Connector
SMA
Connector
B
C
DS50EV401
INPUT
OUTPUT
Figure 2. Test Setup Diagram
OUT+
80%
VO = (OUT+) ± (OUT-)
0V
OUT-
20%
t_R
80%
20%
t_F
Figure 3. CML Output Transition Times
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IN
0V
OUT
t_PLHD
0V
t_PHLD
Figure 4. Propagation Delay Timing Diagram
V_IN
t_ID
t_DI
V_O
Figure 5. Idle Timing Diagram
IN+
0V
IN-
OUT+
0V
OUT-
6
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