DS50EV401_15 Datasheet, PDF (5/19 Pages) Texas Instruments – DS50EV401 2.5 Gbps / 5.0 Gbps or 8.0 Gbps Quad Cable and Backplane Equalizer

DS50EV401
www.ti.com
SNLS288E – JANUARY 2008 – REVISED MARCH 2013
Electrical Characteristics (continued)
Over recommended operating supply and temperature ranges with default register settings unless other specified. ^{(1) (2)}
Symbol
Parameter
Conditions
Min
Typ
Max
Units
CML RECEIVER INPUTS (IN_n+, IN_n-)
V_TX
Input Voltage Swing (Launch
Amplitude)
Measured at point A, AC or DC
coupled, Figure 2
400
1000
1600
mV_P-P
V_IN-S
Input Voltage Sensitivity
AC-Coupled or DC-Coupled
Required Differential Envelope
measured at point B, Figure 2, ⁽⁴⁾,
170
See FR4 / BACKPLANE Typical
Performance Eye Diagrams,
mV_P-P
R_LI
Differential Input Return Loss
100 MHz – 4.0 GHz, with fixture’s
effect de-embedded
10
dB
R_IN
Input Resistance
CML OUTPUTS (OUT_n+, OUT_n-)
Single ended to V_DD
40
50
60
Ω
V_O
Output Voltage Swing
Differential measurement with
OUT_n+ and OUT_n- terminated
by 50Ω to GND AC-Coupled,
800
1000
1200
mV_P-P
Figure 3
V_OCM
Output Common-Mode Voltage
Single-ended measurement DC-
Coupled with 50Ω termination, ⁽⁵⁾
V_DD –
0.25
V
t_R, t_F
Transition Time
20% to 80% of differential output
voltage, measured within 1” from
40
ps
output pins, Figure 3, ⁽⁵⁾
R_O
Output Resistance
Single-ended to V_DD
40
50
60
Ω
R_LO
Differential Output Return Loss
100 MHz – 4.0 GHz, with fixture’s
effect de-embedded. IN_n+ = static
10
dB
high
t_PLHD
Differential Low to High
Propagation Delay
Propagation delay measurement at
50% V_O between input to output,
240
ps
t_PHLD
Differential High to Low
Propagation Delay
100 Mbps, Figure 4, ⁽⁶⁾
240
ps
t_ID
Idle to Valid Differential Data
VIN = 800 mVp-p, 5 Gbps, EIEOS,
40” of 6 mil microstrip FR4,
8
ns
Figure 5, ⁽⁷⁾
t_DI
Valid Differential data to idle
VIN = 800 mVp-p, 5 Gbps, EIOS,
40” of 6 mil microstrip FR4,
8
ns
Figure 5, ⁽⁷⁾
t_CCSK
Inter Pair Channel to Channel
Skew
Difference in 50% crossing
between channels
7
ps
EQUALIZATION
DJ1
Residual Deterministic Jitter at 8 30” of 6 mil microstrip FR4,
Gbps
MODE=0, PRBS-7 (2⁷-1) pattern,
(7) (8)
0.18
UI_P-P
DJ2
Residual Deterministic Jitter at 5 40” of 6 mil microstrip FR4,
Gbps
MODE=1, PRBS-7 (2⁷-1) pattern,
(7) (8)
0.18
0.21
UI_P-P
DJ3
Residual Deterministic Jitter at 2.5 40” of 6 mil microstrip FR4,
Gbps
MODE=1, PRBS-7 (2⁷-1) pattern,
(7) (8)
RJ
Random Jitter
(6) (9)
0.16
0.5
0.18
UI_P-P
psrms
(4) V_IN-S is a measurement of the input differential envelope, see FR4 / BACKPLANE Typical Performance Eye Diagrams. The device does
not require an open eye.
(5) Specification is ensured by characterization at optimal MODE setting and is not tested in production.
(6) Measured with clock-like {11111 00000} pattern.
(7) Specification is ensured by characterization at optimal MODE setting and is not tested in production.
(8) Deterministic jitter is measured at the differential outputs (point C of Figure 2), minus the deterministic jitter before the test channel (point
A of Figure 2). Random jitter is removed through the use of averaging or similar means.
(9) Random jitter contributed by the equalizer is defined as sqrt (J_OUT2 – J_IN2). J_OUT is the random jitter at equalizer outputs in ps-rms, see
point C of Figure 2; J_IN is the random jitter at the input of the equalizer in ps-rms, see point B of Figure 2.
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