DS50EV401_15 Datasheet, PDF (8/19 Pages) Texas Instruments – DS50EV401 2.5 Gbps / 5.0 Gbps or 8.0 Gbps Quad Cable and Backplane Equalizer

DS50EV401
SNLS288E – JANUARY 2008 – REVISED MARCH 2013
FUNCTIONAL DESCRIPTION
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DS50EV401 APPLICATIONS INFORMATION
The DS50EV401 is a programmable quad equalizer optimized for copper backplanes and cables at transmission
rates of 2.5 Gbps up to 8 Gbps. The device consists of an input receive equalizer followed by a limiting amplifier.
The equalizer is designed to open an input eye that is completely closed due to inter-symbol interference (ISI)
induced by the channel interconnect. The equalization is set to keep residual deterministic jitter below 0.2 unit
intervals (UI) regardless of data rate. This equalization scheme allows one equalization setting to satisfy most
serial links between 2.5 and 5.0 Gbps. The DS50EV401 is intended as a unidirectional receiver that should be
placed in close physical proximity to the link end point. Therefore the transmitter does not include de-emphasis
as TX equalization would not be needed over the short distance between the equalizer and the end point.
VDD VDD
1/4 DS50EV401
DC Offset Correction
VDD VDD
IN_n+
IN_n-
Input Termination
Equalizer
Limiting
Amplifier
Signal Detect
CML
Driver
Output Termination
OUT_n+
OUT_n-
Figure 7. General Block Diagram
Data Channels
The DS50EV401 consists of four data channels. Each channel provides input termination, receiver equalization,
signal limiting, offset cancellation, and a CML output driver, as shown in Figure 7. The data channels support two
levels of equalization, controlled by the pin MODE. The equalization levels are set simultaneously on all 4
channels, as described in Table 1.
When an idle condition is sensed on a channel’s input, the transmit driver is automatically placed into electrical
idle mode. The common mode voltage is set, and the differential output is forced to zero. To save power, the
output driver current is powered off when the device is in electrical idle mode. All other circuits maintain their bias
currents allowing a fast recovery from idle to the active state. Electric idle is performed on a per channel basis,
and several channels can be in idle while others are actively passing data.
6 mil microstrip FR4
trace length (in)
0–30
0–40
Table 1. MODE Control Table
24 AWG Twin-AX cable
length (m)
0–7
0–10
Frequency
8 Gbps
2.5 Gbps
5.0 Gbps
Channel Loss
16 dB
14 dB
20 dB
MODE
0
1
8
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