DS50EV401_15 Datasheet, PDF (10/19 Pages) Texas Instruments – DS50EV401 2.5 Gbps / 5.0 Gbps or 8.0 Gbps Quad Cable and Backplane Equalizer

DS50EV401
SNLS288E – JANUARY 2008 – REVISED MARCH 2013
3V3
10 PF
VDD
VDD
VDD
IN_0+
IN_0-
IN_1+
IN_1-
IN_2+
IN_2-
IN_3+
IN_3-
EN0
EN1
EN2
EN3
MODE: Tie High or
Low or drive.
(Speed Select)
MODE
DS50EV401
Quad EQUALIZER
VDD
VDD
VDD
3V3
10 PF
All Bypass CAPS
0.1 PF unless noted.
OUT_0+
OUT_0-
OUT_1+
OUT_1-
OUT_2+
OUT_2-
OUT_3+
OUT_3-
SD0
SD1
SD2
SD3
Reserv
www.ti.com
GND
Figure 8. Typical Interface Circuit
The CML inputs are AC coupled to the device as shown in Figure 8. Internal to the device are 50Ω terminations
to V_DD.
The CML outputs drive 100 Ω transmission lines and are AC coupled and terminated at their load.
The ENABLE inputs and SIGNAL DETECT outputs are optional. Internal to the device the signal detect circuity is
connected to the enable circuit providing the automatic power management feature. When the No-signal
condition is detected, the respective channel is placed in standby mode. The MODE pin is used to select
between low and high data rate equalization settings. Depending upon the application it may be tied High, tied
Low, or driven. There are several reserved pins on the device, these are NC pins and should be left open.
Power is supplied through six V_DD pins to the device. A 0.1µF capacitor is recommended per pin as close to the
device as possible. A larger bulk capacitor is also recommended to be placed near by the device. Ground is
supplied to the device via the ground pins and also the DAP.
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