DS50EV401_15 Datasheet, PDF (3/19 Pages) Texas Instruments – DS50EV401 2.5 Gbps / 5.0 Gbps or 8.0 Gbps Quad Cable and Backplane Equalizer

DS50EV401
www.ti.com
Pin Name
OTHER
Reserv
Pin Number
16, 17, 18,
19, 20, 21,
23, 37, 47,
48
I/O, Type
SNLS288E – JANUARY 2008 – REVISED MARCH 2013
PIN DESCRIPTIONS (continued)
Description
Reserved. Do not connect. Leave open.
Connection Diagram
IN_0+ 1
IN_0- 2
VDD 3
IN_1+ 4
IN_1- 5
VDD 6
VDD 7
IN_2+ 8
IN_2- 9
VDD 10
IN_3+ 11
IN_3- 12
DS50EV401
TOP VIEW
(not to scale)
DAP = GND
36 OUT_0+
35 OUT_0-
34 GND
33 OUT_1+
32 OUT_1-
31 GND
30 GND
29 OUT_2+
28 OUT_2-
27 GND
26 OUT_3+
25 OUT_3-
Figure 1. TOP VIEW — Not to scale
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
Copyright © 2008–2013, Texas Instruments Incorporated
Product Folder Links: DS50EV401
Submit Documentation Feedback
3