DRV8305_16 Datasheet, PDF (9/59 Pages) Texas Instruments – Three Phase Gate Driver

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DRV8305
SLVSCX2B – AUGUST 2015 – REVISED FEBRUARY 2016
Electrical Characteristics (continued)
PVDD = 4.4 to 45 V, T_A = 25°C, unless specified under test condition
PARAMETER
TEST CONDITIONS
LOW SIDE (GLA, GLB, GLC) PEAK CURRENT GATE DRIVE
IDRIVEP_HS = 0000
IDRIVEP_HS = 0001
IDRIVEP_HS = 0010
IDRIVEP_HS = 0011
IDRIVEP_HS = 0100
I_{DRIVEP_LS}
Low-side peak source
current
IDRIVEP_HS = 0101
IDRIVEP_HS = 0110
IDRIVEP_HS = 0111
IDRIVEP_HS = 1000
IDRIVEP_HS = 1001
IDRIVEP_HS = 1010
IDRIVEP_HS = 1011
IDRIVEP_HS = 1100, 1101, 1110, 1111
LOW SIDE (GLA, GLB, GLC) PEAK CURRENT GATE DRIVE
IDRIVEN_HS = 0000
IDRIVEN_HS = 0001
IDRIVEN_HS = 0010
IDRIVEN_HS = 0011
IDRIVEN_HS = 0100
IDRIVEN_HS = 0101
I_{DRIVEN_LS}
Low-side peak sink current IDRIVEN_HS = 0110
IDRIVEN_HS = 0111
IDRIVEN_HS = 1000
IDRIVEN_HS = 1001
IDRIVEN_HS = 1010
IDRIVEN_HS = 1011
IDRIVEN_HS = 1100, 1101, 1110, 1111
GATE PULL DOWN, MOTOR OFF STATE (BRIDGE IN HI-Z)
R_{SLEEP_PD}
Gate pulldown resistance,
SLEEP, undervoltage and
sleep mode
2 V < PVDD < PVDD_UVLO2
GHX to GND; GLX to GND
R_{STANDBY_PD}
I_{OPERATING_PD}
Gate pulldown resistance,
STANDBY, standby mode
(Parallel with I_{STANDBY_PD})
Gate pulldown current,
OPERATING, operating
mode
PVDD > PVDD_UVLO2; EN_GATE =
low;
GHX to GND; GLX to GND
PVDD > PVDD_UVLO2; EN_GATE =
high;
GHX to SHX; GLX to SLX
GATE PULL DOWN, MOTOR ON STATE (IDRIVE/tdrive)
I_HOLD
Gate pulldown current,
holding
PVDD > PVDD_UVLO2; EN_GATE =
high;
GHX to SHX; GLX to SLX
I_PULLDOWN
Gate pulldown current,
strong
PVDD > PVDD_UVLO2; EN_GATE =
high;
GHX to SHX; GLX to SLX
MIN
TYP
0.01
0.02
0.03
0.04
0.05
0.06
0.07
0.125
0.25
0.5
0.75
1
0.05
0.02
0.03
0.04
0.05
0.06
0.07
0.08
0.25
0.5
0.75
1
1.25
0.06
2000
750
50
MAX UNIT
A
A
Ω
Ω
mA
50
mA
1.25
A
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