DRV8305_16 Datasheet, PDF (31/59 Pages) Texas Instruments – Three Phase Gate Driver

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DRV8305
SLVSCX2B – AUGUST 2015 – REVISED FEBRUARY 2016
7.3.9.3 MCU Watchdog
The DRV8305 incorporates an MCU watchdog function to ensure that the external controller that is instructing
the device is active and not in an unknown state. The MCU watchdog function may be enabled by writing a 1 to
the WD_EN setting in the SPI register 0x9. bit D3. The default setting for the device is with the watchdog
disabled. When the watchdog is enabled, an internal timer starts to countdown to the interval set by the WD_DLY
setting in the SPI register 0x9, bits D6-D5. To restart the watchdog timer, the address 0x1 (status register) must
be read by the controller within the interval set by the WD_DLY setting. If the watchdog timer is allowed to expire
without the address 0x1 being read, a watchdog fault will be enabled.
Response to a watchdog fault is as follows:
• A latched fault occurs on the DRV8305 and the gate drivers are put into a safe state. An appropriate recovery
sequence must then be performed.
• The PWRGD pin is taken low for 56 µs and then back high in order to reset the controller or indicate the
watchdog fault
• The nFAULT pin is asserted low, the WD_EN bit is cleared, and the WD_FAULT set high in register 0x3, bit
D9
• It is recommended to read the status registers as part of the recovery or power-up routine in order to
determine whether a WD_FAULT had previously occurred
Note that the watchdog fault results in a clearing of the WD_EN setting and it will have to be set again to resume
watchdog functionality.
7.3.9.4 VREG Undervoltage (VREG_UV)
The DRV8305 has an undervoltage monitor on the VREG output regulator to ensure the external controller does
not experience a brownout condition. The undervoltage monitor will signal a fault if the VREG output drops below
a set threshold from its set point. The VREG output set point is configured for two different levels, 3.3 V or 5 V,
depending on the DRV8305 device options (DRV83053Q and DRV83055Q). The VREG undervoltage level can
be set through the SPI setting VREG_UV_LEVEL in register 0xB, bits D1-D0. The VREG undervoltage monitor
can be disabled through the SPI setting DIS_VREG_PWRGD in register 0xB, bit D2.
Response to a VREG undervoltage fault is as follows:
• A latched fault occurs on the DRV8305 and the gate drivers are put into a safe state. An appropriate recovery
sequence must then be performed.
• The PWRGD is taken low until the undervoltage condition is removed and for at least a minimum of 56 µs.
• The nFAULT pin is asserted low and the VREG_UV bit set high in register 0x3, bit D6.
• The fault can be cleared after the VREG undervoltage condition is removed with CLR_FLTS or an EN_GATE
reset pulse
Note that the VREG undervoltage monitor is disabled on the no regulator (VREF) device option (DRV8305NQ
and DRV8305NE).
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