DRV8305_16 Datasheet, PDF (27/59 Pages) Texas Instruments – Three Phase Gate Driver

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DRV8305
SLVSCX2B – AUGUST 2015 – REVISED FEBRUARY 2016
INx_x
Gx_x
1 _{Input Signal}
2 _{Output Slew}
3 _{Expiration of Blanking}
tDead
tBLANK
1
2
3
tdeglitch
Figure 13. V_DS Deglitch and Blank Diagram
The DRV8305 has three possible responses to a V_DS overcurrent event. This response is set through the SPI
VDS_MODE setting in register 0xC, bits D2-D0.
• V_DS Latched Shutdown Mode:
When a V_DS overcurrent event occurs, the device will pull all gate drive outputs low in order to put all six
external MOSFETs into high impedance mode. The fault will be reported on the nFAULT pin with the specific
MOSFET in which the overcurrent event was detected in reported through the SPI status registers.
• V_DS Report Only Mode:
In this mode, the device will take no action related to the gate drivers. When the overcurrent event is detected
the fault will be reported on the nFAULT pin with the specific MOSFET in which the overcurrent event was
detected in reported through the SPI status registers. The gate drivers will continue to operate normally.
• V_DS Disabled Mode:
The device ignores all the V_DS overcurrent event detections and does not report them.
7.3.8.3.1 MOSFET dV/dt Turn On Protection (TDRIVE)
The DRV8305 gate driver implements a strong pulldown scheme during turn on of the opposite MOSFET for
preventing parasitic dV/dt turn on. Parasitic dV/dt turn on can occur when charge couples into the gate of the
low-side MOSFET during a switching event. If the charge induces enough voltage to cross the threshold of the
low-side MOSFET shoot-through can occur in the half-bridge. To prevent this the TDRIVE: Gate Driver State
Machine state machine turns on a strong pulldown during switching. After the switching event has completed, the
gate driver switches back to a lower hold off pull down to improve efficiency.
7.3.8.3.2 MOSFET Gate Drive Protection (GDF)
The DRV8305 uses a multilevel scheme to protect the external MOSFET from V_GS voltages that could damage it.
The first stage uses integrated V_GS clamps that will turn on when the GHx voltage exceeds the SHx voltage by a
value that could be damaging to the external MOSFETs.
The second stage relies on the TDRIVE state machine to detect when abnormal conditions are present on the
gate driver outputs. After the TDRIVE timer has expired the gate driver performs a check of the gate driver
outputs against the commanded input. If the two do not match a gate drive fault (FETXX_VGS) is reported. This
can be used to detected gate short to ground or gate short to supply event. The TDRIVE timer is adjustable for
the high-side and low-side gate drive outputs through the TDRIVEN setting in register 0x5, bits D9-D8 and the
TDRIVEP setting in register 0x6, bits D9-D8. The gate fault detection through TDRIVE can be disabled through
the DIS_GDRV_FAULT setting in register 0x9, bit D8.
The third stage uses undervoltage monitors for the low-side gate drive regulator (VCP_LSD_UVLO2) and high-
side gate drive charge pump (VCPH_UVLO2) and an overvoltage monitor for high-side charge pump
(VCPH_OVLO). These monitors are used to detect if any of the power supplies to the gate drivers have
encountered an abnormal condition.
7.3.8.4 Low-Side Source Monitors (SNS_OCP)
In additional to the V_DS monitors across each MOSFET, the DRV8305 directly monitors the voltage on the SLx
pins with respect to ground. If high current events such phase shorts cause the SLx pin voltage to exceed 2 V,
the DRV8305 will shutdown the gate driver, put the external MOSFETs into a high impedance state, and report a
SNS_OCP fault error on the nFAULT pin and corresponding SPI status bit in register 0x2, bits D2-D0.
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