DRV8305_16 Datasheet, PDF (18/59 Pages) Texas Instruments – Three Phase Gate Driver

DRV8305
SLVSCX2B – AUGUST 2015 – REVISED FEBRUARY 2016
MCU PWM
MCU PWM
MCU PWM
INHA
INLA
INHB
INLB
INHC
INLC
3-PWM
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Figure 7. 3-PWM Mode
• Table 3 and Table 4 show the truth tables for the 1-PWM input mode. The 1-PWM mode uses an internally
stored 6-step block commutation table to control the outputs of the three half-bridge drivers based on one
PWM and three GPIO inputs. This mode allows the use of a lower cost microcontroller by requiring only one
PWM resource. The PWM signal is applied on pin INHA (PWM_IN) to set the duty cycle of the half-bridge
outputs along with the three GPIO signals on pins INLA (PHC_0), INHB (PHC_1), INLB (PHC_2) that serve to
set the value of a three bit register for the commutation table. The PWM may be operated from 0-100% duty
cycle. The three bit register is used to select the state for each half-bridge for a total of eight states including
an align and stop state.
An additional and optional GPIO, INHC (DWELL) can be used to facilitate the insertion of dwell states or
phase current overlap states between the six commutation steps. This may be used to reduce acoustic noise
and improve motion through the reduction of abrupt current direction changes when switching between states.
INHC must be high when the state is changed and the dwell state will exist until INHC is taken low. If the
dwell states are not being used, the INHC pin can be tied low.
In 1-PWM mode all activity on INLC is ignored.
MCU PWM
MCU GPIO
MCU GPIO
MCU GPIO
MCU GPIO
(optional)
INHA
INLA
INHB
INLB
INHC
INLC
1 PWM
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Figure 8. 1-PWM Mode
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