TM4C1299NCZAD Datasheet, PDF (858/2017 Pages) Texas Instruments – Tiva Microcontroller

External Peripheral Interface (EPI)
Table 11-10. PSRAM Fixed Latency Wait State Configuration
Latency Counter
BCR Code 2
BCR Code 3
BCR Code 4
BCR Code 5
BCR Code 6
BCR Code 8
Latency in Clocks
3
4
5
6
7
9
RDWS[1:0]/WRWS[1:0]
0x0
0x1
0x1
0x2
0x2
0x3
RWSM/WRWSM
0
1
0
1
0
0
In variable initial latency mode, the memory's WAIT (iRDY) pin guides the EPI module when to read
and write. The WAIT (iRDY) pin stalls the access for the duration of the latency and adds cycles if
there is a refresh collision. To get the best performance, set CR[13:11] = 0x2, the WRWS field of
the EPIHB16CFG register to 0x0, and the WRWSM and RDWSM bit of the EPI16TIMEn register to 0.
For the WAIT pin to be recognized correctly set the IRDYDLY bit in the EPI16TIMEn register to 1
and the CR[8] =1 in the EPIHBPSRAM register.
Note: Wait state latency works differently in PSRAM Burst mode than in other modes. In PSRAM
Burst mode the RDWS and WRWS bit fields define the latency for only the first access of the
write or read cycle. Every access after that is a single access.
Figure 11-7 on page 858 and Figure 11-8 on page 859 depict a PSRAM burst read and write.
Figure 11-7. PSRAM Burst Read
EPICLK
EPI0S31
EPI0S[19:0]
ALE
CSn
RDn
WRn
EPI0S29
iRDY
EPI0S32
EPI0S[15:0]
BSELn
ADDRESS
Latency (3 clocks)
DATA0 DATA1 DATA2 DATA3
858
June 18, 2014
Texas Instruments-Production Data