TM4C1299NCZAD Datasheet, PDF (690/2017 Pages) Texas Instruments – Tiva Microcontroller

Internal Memory
Register 68: Boot Configuration (BOOTCFG), offset 0x1D0
Note: Offset is relative to System Control base address of 0x400F.E000.
Note: The Boot Configuration (BOOTCFG) register requires a POR before the committed
changes take effect.
This register is not written directly, but instead uses the FMD register as explained in “Non-Volatile
Register Programming-- Flash Memory Resident Registers” on page 629. When this register is
committed, the new value cannot be read back until after the power cycle. This register provides
configuration of a GPIO pin to enable the ROM Boot Loader as well as a write-once mechanism to
disable external debugger access to the device. At reset, the user has the opportunity to direct the
core to execute the ROM Boot Loader or the application in Flash memory by using any GPIO signal
from Ports A through H as configured by the bits in this register. At reset, the following sequence is
performed:
1. The BOOTCFG register is read. If the EN bit is clear, the ROM Boot Loader is executed.
2. In the ROM Boot Loader, the status of the specified GPIO pin is compared with the specified
polarity. If the status matches the specified polarity, the ROM is mapped to address 0x0000.0000
and execution continues out of the ROM Boot Loader.
3. If the EN bit is set or the status doesn't match the specified polarity, the data at address
0x0000.0004 is read, and if the data at this address is 0xFFFF.FFFF, the ROM is mapped to
address 0x0000.0000 and execution continues out of the ROM Boot Loader.
4. If there is data at address 0x0000.0004 that is not 0xFFFF.FFFF, the stack pointer (SP) is loaded
from Flash memory at address 0x0000.0000 and the program counter (PC) is loaded from
address 0x0000.0004. The user application begins executing.
The DBG0 bit is cleared by the factory and the DBG1 bit is set, which enables external debuggers.
Clearing the DBG1 bit disables any external debugger access to the device, starting with the next
power-up cycle of the device. The NW bit indicates that bits in the register can be changed from 1
to 0.
By committing the register values using the COMT bit in the FMC register, the register contents
become non-volatile and are therefore retained following power cycling. Prior to being committed,
bits can only be changed from 1 to 0. The reset value shown only applies to power-on reset when
the register is not yet committed; any other type of reset does not affect this register. Once committed,
the register retains its value through power-on reset. Once committed, the only way to restore the
factory default value of this register is to perform the sequence detailed in “Recovering a "Locked"
Microcontroller” on page 217.
Boot Configuration (BOOTCFG)
Base 0x400F.E000
Offset 0x1D0
Type RO, reset 0xFFFF.FFFE
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
NW
reserved
Type RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
Reset
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
PORT
PIN
POL
EN
reserved
KEY
reserved
DBG1 DBG0
Type RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
Reset
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
690
June 18, 2014
Texas Instruments-Production Data