TM4C1299NCZAD Datasheet, PDF (43/2017 Pages) Texas Instruments – Tiva Microcontroller

Tiva^™ TM4C1299NCZAD Microcontroller
Register 85: Ethernet PHY Address or Data - MR14 (EPHYADDAR), address 0x00E .......................... 1637
Register 86: Ethernet PHY Status - MR16 (EPHYSTS), address 0x010 .............................................. 1638
Register 87: Ethernet PHY Specific Control- MR17 (EPHYSCR), address 0x011 ................................ 1641
Register 88: Ethernet PHY MII Interrupt Status 1 - MR18 (EPHYMISR1), address 0x012 .................... 1644
Register 89: Ethernet PHY MII Interrupt Status 2 - MR19 (EPHYMISR2), address 0x013 .................... 1647
Register 90: Ethernet PHY False Carrier Sense Counter - MR20 (EPHYFCSCR), address 0x014 ........ 1650
Register 91: Ethernet PHY Receive Error Count - MR21 (EPHYRXERCNT), address 0x015 ............... 1651
Register 92: Ethernet PHY BIST Control - MR22 (EPHYBISTCR), address 0x016 .............................. 1652
Register 93: Ethernet PHY LED Control - MR24 (EPHYLEDCR), address 0x018 ................................ 1655
Register 94: Ethernet PHY Control - MR25 (EPHYCTL), address 0x019 ............................................. 1656
Register 95: Ethernet PHY 10Base-T Status/Control - MR26 (EPHY10BTSC), address 0x01A ............ 1658
Register 96: Ethernet PHY BIST Control and Status 1 - MR27 (EPHYBICSR1), address 0x01B ........... 1660
Register 97: Ethernet PHY BIST Control and Status 2 - MR28 (EPHYBICSR2), address 0x01C .......... 1661
Register 98: Ethernet PHY Cable Diagnostic Control - MR30 (EPHYCDCR), address 0x01E ............... 1662
Register 99: Ethernet PHY Reset Control - MR31 (EPHYRCR), address 0x01F .................................. 1663
Register 100: Ethernet PHY LED Configuration - MR37 (EPHYLEDCFG), address 0x025 ..................... 1664
LCD Controller ........................................................................................................................... 1675
Register 1: LCD PID Register Format (LCDPID), offset 0x000 ......................................................... 1699
Register 2: LCD Control (LCDCTL), offset 0x004 ............................................................................ 1700
Register 3: LCD LIDD Control (LCDLIDDCTL), offset 0x00C ............................................................ 1702
Register 4: LCD LIDD CS0 Configuration (LIDDCS0CFG), offset 0x010 ........................................... 1705
Register 5: LIDD CS0 Read/Write Address (LIDDCS0ADDR), offset 0x014 ...................................... 1706
Register 6: LIDD CS0 Data Read/Write Initiation (LIDDCS0DATA), offset 0x018 ............................... 1707
Register 7: LIDD CS1 Configuration (LIDDCS1CFG), offset 0x01C .................................................. 1708
Register 8: LIDD CS1 Address Read/Write Initiation (LIDDCS1ADDR), offset 0x020 ......................... 1709
Register 9: LIDD CS1 Data Read/Write Initiation (LIDDCS1DATA), offset 0x024 ............................... 1710
Register 10: LCD Raster Control (LCDRASTRCTL), offset 0x028 ...................................................... 1711
Register 11: LCD Raster Timing 0 (LCDRASTRTIM0), offset 0x02C ................................................... 1715
Register 12: LCD Raster Timing 1 (LCDRASTRTIM1), offset 0x030 ................................................... 1716
Register 13: LCD Raster Timing 2 (LCDRASTRTIM2), offset 0x034 ................................................... 1717
Register 14: LCD Raster Subpanel Display 1 (LCDRASTRSUBP1), offset 0x038 ................................ 1720
Register 15: LCD Raster Subpanel Display 2 (LCDRASTRSUBP2), offset 0x03C ............................... 1721
Register 16: LCD DMA Control (LCDDMACTL), offset 0x040 ............................................................. 1722
Register 17: LCD DMA Frame Buffer 0 Base Address (LCDDMABAFB0), offset 0x044 ....................... 1724
Register 18: LCD DMA Frame Buffer 0 Ceiling Address (LCDDMACAFB0), offset 0x048 .................... 1725
Register 19: LCD DMA Frame Buffer 1 Base Address (LCDDMABAFB1), offset 0x04C ....................... 1726
Register 20: LCD DMA Frame Buffer 1 Ceiling Address (LCDDMACAFB1), offset 0x050 .................... 1727
Register 21: LCD System Configuration Register (LCDSYSCFG), offset 0x054 .................................. 1728
Register 22: LCD Interrupt Raw Status and Set Register (LCDRISSET), offset 0x058 ......................... 1730
Register 23: LCD Interrupt Status and Clear (LCDMISCLR), offset 0x05C .......................................... 1733
Register 24: LCD Interrupt Mask (LCDIM), offset 0x060 .................................................................... 1736
Register 25: LCD Interrupt Enable Clear (LCDIENC), offset 0x064 ..................................................... 1739
Register 26: LCD Clock Enable (LCDCLKEN), offset 0x06C .............................................................. 1742
Register 27: LCD Clock Resets (LCDCLKRESET), offset 0x070 ........................................................ 1743
Analog Comparators ................................................................................................................. 1744
Register 1: Analog Comparator Masked Interrupt Status (ACMIS), offset 0x000 ................................ 1751
Register 2: Analog Comparator Raw Interrupt Status (ACRIS), offset 0x004 ..................................... 1752
Register 3: Analog Comparator Interrupt Enable (ACINTEN), offset 0x008 ....................................... 1753
June 18, 2014
43
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