TM4C1299NCZAD Datasheet, PDF (1443/2017 Pages) Texas Instruments – Tiva Microcontroller

Tiva^™ TM4C1299NCZAD Microcontroller
Table 20-8. Enhanced Receive Descriptor 0 (RDES0) (continued)
Bit
Description
7 Timestamp Available or Giant Frame
When Advanced Timestamp feature is enabled, this bit indicates that a snapshot of the Timestamp is written in
descriptor words 6 (RDES6) and 7 (RDES7). This is valid only when the Last Descriptor bit (RDES0[8]) is set.
Otherwise, this bit, when set, indicates the Giant Frame Status. Giant frames are larger than 1,518-byte (or
1,522-byte for VLAN or 2,000-byte when Bit 27 of MAC Configuration register is set) normal frames and larger
than 9,018-byte (9,022-byte for VLAN) frame when Jumbo Frame processing is enabled.
6 LC: Late Collision
When set, this bit indicates that a late collision has occurred while receiving the frame in half-duplex mode.
5 FT: Frame Type
When set, this bit indicates that the Receive Frame is an Ethernet-type frame (the LT field is greater than or equal
to 1,536). When this bit is reset, it indicates that the received frame is an IEEE 802.3 frame. This bit is not valid
for Runt frames less than 14 bytes. In addition when the IPC bit is set in the EMACCFG register, this bit conveys
different information. See Table 20-9 on page 1443.
4 RWT: Receive Watchdog Timeout
When set, this bit indicates that the Receive Watchdog Timer has expired while receiving the current frame and
the current frame is truncated after the Watchdog Timeout.
3 RE: Receive Error
When set, this bit indicates that an error occurred during frame reception.
2 DE: Dribble Bit Error
When set, this bit indicates that the received frame has a non-integer multiple of bytes (odd nibbles).
1 CE: CRC Error
When set, this bit indicates that a Cyclic Redundancy Check (CRC) Error occurred on the received frame. This
field is valid only when the Last Descriptor bit (RDES0[8]) is set.
0 Extended Status Available/RX MAC Address
When set, this bit indicates that the extended status is available in descriptor word 4 (RDES4). This is valid only
when the Last Descriptor bit (RDES0[8]) is set. This bit is invalid when Bit 30 is set.
Table 20-9 on page 1443 shows the frame information conveyed in bits 7, 5, and 0 of RDES0 when
the Checksum Offload Engine is enabled and disabled through the IPC bit in the EMACCFG register.
Table 20-9. RDES0 Checksum Offload bits
Bit 5:
Frame
Type
0
1
1
1
1
0
0
0
Bit 7: IPC Bit 0: Payload IPC bit value
Checksum Checksum in EMACCFG
Error
Error
register
Frame Status
0
0
X
IEEE 802.3 Type frame (Length field value is less than 1,536).
This status definition is valid even when the Checksum Offload
engine is disabled.
0
0
0
IPv4/IPv6 Type frame in which no checksum error is detected.
0
0
1
The frame is an IEEE 802.3 Type frame (Length field value is
greater than or equal to 1,536).
0
1
1
IPv4/IPv6 Type frame with a payload checksum error detected
1
1
1
IPv4/IPv6 Type frame with both IP header and payload
checksum errors detected
0
1
1
IPv4/IPv6 Type frame with no IP header checksum error and
the payload check bypassed, due to an unsupported payload
1
1
1
A Type frame that is neither IPv4 or IPv6 (the Checksum Offload
engine bypasses checksum completely.)
1
0
X
Reserved
June 18, 2014
Texas Instruments-Production Data
1443