TM4C1299NCZAD Datasheet, PDF (1355/2017 Pages) Texas Instruments – Tiva Microcontroller

Tiva^™ TM4C1299NCZAD Microcontroller
Bit/Field
4
3
2
1
0
Name
QCMDST
OAR2SEL
FBR
TREQ
RREQ
Type
RC
RO
RO
RO
RO
Reset
0
Description
Quick Command Status
Value Description
0 The last transaction was a normal transaction or a transaction
has not occurred.
1 The last transaction was a Quick Command transaction.
0
OAR2 Address Matched
Value Description
0 Either the address is not matched or the match is in legacy
mode.
1 OAR2 address matched and ACKed by the slave.
This bit gets reevaluated after every address comparison.
0
First Byte Received
Value Description
0 The first byte has not been received.
1 The first byte following the slave's own address has been
received.
This bit is only valid when the RREQ bit is set and is automatically cleared
when data has been read from the I2CSDR register.
Note: This bit is not used for slave transmit operations.
0
Transmit Request
Value Description
0 No outstanding transmit request.
1
The I²C controller has been addressed as a slave transmitter
and is using clock stretching to delay the master until data has
been written to the I2CSDR register.
0
Receive Request
Value Description
0 No outstanding receive data.
1
The I²C controller has outstanding receive data from the I²C
master and is using clock stretching to delay the master until
the data has been read from the I2CSDR register.
June 18, 2014
Texas Instruments-Production Data
1355