TM4C1299NCZAD Datasheet, PDF (551/2017 Pages) Texas Instruments – Tiva Microcontroller

Tiva^™ TM4C1299NCZAD Microcontroller
7.3.1
7.3.2
clock (RTC) when the system clock is powered down. Hibernate mode can be entered through one
of two ways:
■ The user initiates hibernation by setting the HIBREQ bit in the Hibernation Control (HIBCTL)
register
■ Power is arbitrarily removed from V_DD while a valid V_BAT is applied
Once in hibernation, the module signals an external voltage regulator to turn the power back on
when an external pin (WAKE, RST or a wake-enabled GPIO pin) is asserted or when the internal
RTC reaches a certain value. The Hibernation module can also detect when the battery voltage is
low and optionally prevent hibernation or wake from hibernation when the battery voltage falls below
a certain threshold. Note that multiple wake sources can be configured at the same time to generate
a wake signal such that any of them can wake the module.
When waking from hibernation, the HIB signal is deasserted. The return of V_DD causes a POR to
be executed. The time from when the WAKE signal is asserted to when code begins execution is
equal to the wake-up time (t_{WAKE_TO_HIB}) plus the power-on reset time (T_POR).
Register Access Timing
Because the Hibernation module has an independent clocking domain, hibernation registers must
be written only with a timing gap between accesses. The delay time is t_{HIB_REG_ACCESS}, therefore
software must guarantee that this delay is inserted between back-to-back writes to Hibernation
registers or between a write followed by a read. The WC interrupt in the HIBMIS register can be used
to notify the application when the Hibernation modules registers can be accessed. Alternatively,
software may make use of the WRC bit in the Hibernation Control (HIBCTL) register to ensure that
the required timing gap has elapsed. This bit is cleared on a write operation and set once the write
completes, indicating to software that another write or read may be started safely. Software should
poll HIBCTL for WRC=1 prior to accessing any hibernation register.
Back-to-back reads from Hibernation module registers have no timing restrictions. Reads are
performed at the full peripheral clock rate.
Hibernation Clock Source
The HIB module can be clocked by one of three different clock sources:
■ A 32.768-kHz oscillator
■ An external 32.768-kHz clock source
■ An internal low frequency oscillator (HIB LFIOSC)
Table 7-2 on page 552 summarizes the encodings for the bits in the HIBCTL register that are required
for each clock source to be enabled. Note that CLK32EN must be set for any Hibernation clock
source to be valid. The Hibernation module is not enabled until the CLK32EN bit is set. The HIB
clock source is the source of the RTC Oscillator (RTCOSC), which can be selected as the system
clock source by programming a 0x4 in the OSCSRC field of the Run and Sleep Mode Configuration
(RSCLKCFG) register in the System Control Module. Please refer to “System Control” on page 224
for more information.
June 18, 2014
551
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