TMS320DM6435ZWT6 Datasheet, PDF (82/252 Pages) Texas Instruments – Digital Media Processor

TMS320DM6435
Digital Media Processor
SPRS344C – NOVEMBER 2006 – REVISED JUNE 2008
www.ti.com
3.6.2 Peripheral Selection After Device Reset
After device reset, most peripheral configurations are done within the peripheral’s registers. This section
discusses some additional peripheral controls in the System Module. For information on multiplexed pin
controls that determine what peripheral pins are brought out to the pins, see Section 3.7, Multiplexed Pin
Configurations.
3.6.2.1 HPI Control Register (HPICTL)
The HPI Control (HPICTL) register determines the Host Burst Write Time-Out value. The user should
only modify this register once during device initialization. When modifying this register, the user
must ensure the HPI FIFOs are empty and there are no on-going HPI transactions.
31
16
RESERVED
R-0000 0000 0000 0000
15
10
9
8
7
0
RESERVED
RESERVED
R- 0000 00
R/W-00
LEGEND: R = Read; W = Write; -n = value after reset
TIMOUT
R/W-1000 0000
Figure 3-8. HPICTL Register— 0x01C4 0030
Bit
31:10
9:8
7:0
Table 3-16. HPICTL Register Description
Field Name Description
RESERVED Reserved. Read-only, writes have no effect.
RESERVED Reserved. For proper device operation, the user should only write "0" to these bits (default).
TIMOUT
Host Burst Write Timeout Value
When the HPI time-out counter reaches the value programmed here, the HPI write FIFO content is flushed. For
more details on the time-out counter and its use in write bursting, see the TMS320DM643x DMP Host Port
Interface (HPI) User's Guide (literature number SPRU998).
3.6.2.2 Timer Control Register (TIMERCTL)
The Timer Control Register (TIMERCTL) provides additional control for Timer0 and Timer2. The user
should only modify this register once during device initialization, when the corresponding Timer is
not in use.
• Timer 2 Control: The TIMERCTL.WDRST bit determines if the WatchDog timer event (Timer 2) can
cause a device max reset. For more details on the description of a maximum reset, see Section 6.5.3,
Maximum Reset.
• Timer 0 Control: The TINP0SEL bit selects the clock source connected to Timer0's TIN0 input.
31
16
RESERVED
R-0000 0000 0000 0000
15
2
1
0
RESERVED
TINP0
SEL
WD
RST
R- 0000 0000 0000 00
R/W-0 R/W-1
LEGEND: R = Read; W = Write; -n = value after reset
Figure 3-9. TIMERCTL Register— 0x01C4 0084
82
Device Configuration
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