TMS320DM6435ZWT6 Datasheet, PDF (194/252 Pages) Texas Instruments – Digital Media Processor

TMS320DM6435
Digital Media Processor
SPRS344C – NOVEMBER 2006 – REVISED JUNE 2008
6.13 Host-Port Interface (HPI) Peripheral
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6.13.1 HPI Device-Specific Information
The DM6435 device includes a user-configurable 16-bit Host-port interface (HPI16).
Software handshaking via the HRDY bit of the Host Port Control Register (HPIC) is not supported on the
DM6435.
The DM6435 HPI does not support the HAS feature. For proper device operation, the HAS pin must be
pulled up via an external resistor.
6.13.2 HPI Peripheral Register Description(s)
Table 6-46. HPI Control Registers
HEX ADDRESS RANGE
01C6 7800
01C6 7804
01C6 7808 - 01C6 7824
01C6 7828
01C6 782C
01C6 7830
01C6 7834
01C6 7838
01C6 780C - 01C6 7FFF
ACRONYM
PID
PWREMU_MGMT
-
-
-
HPIC
HPIA
(HPIAW) ⁽¹⁾
HPIA
(HPIAR) ⁽¹⁾
-
REGISTER NAME
Peripheral Identification Register
HPI power and emulation management register
Reserved
Reserved
Reserved
HPI control register
HPI address register
(Write)
HPI address register
(Read)
Reserved
COMMENTS
The CPU has read/write
access to the
PWREMU_MGMT register.
The Host and the CPU both
have read/write access to the
HPIC register.
The Host has read/write
access to the HPIA registers.
The CPU has only read
access to the HPIA registers.
(1) There are two 32-bit HPIA registers: HPIAR for read operations and HPIAW for write operations. The HPI can be configured such that
HPIAR and HPIAW act as a single 32-bit HPIA (single-HPIA mode) or as two separate 32-bit HPIAs (dual-HPIA mode) from the
perspective of the Host. The CPU can access HPIAW and HPIAR independently. For more details about the HPIA registers and their
modes, see the TMS320C643x DMP Host Port Interface (HPI) User's Guide (literature number SPRU998).
194 Peripheral Information and Electrical Specifications
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