TMS320DM6435ZWT6 Datasheet, PDF (200/252 Pages) Texas Instruments – Digital Media Processor

TMS320DM6435
Digital Media Processor
SPRS344C – NOVEMBER 2006 – REVISED JUNE 2008
6.14.2 McBSP Electrical Data/Timing
6.14.2.1 Multichannel Buffered Serial Port (McBSP) Timing
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Table 6-50. Timing Requirements for McBSP⁽¹⁾ (see Figure 6-29)
NO.
2
t_c(CKRX)
3
t_w(CKRX)
5
t_su(FRH-CKRL)
6
t_h(CKRL-FRH)
7
t_su(DRV-CKRL)
8
t_h(CKRL-DRV)
10
t_su(FXH-CKXL)
11
t_h(CKXL-FXH)
Cycle time, CLKR/X
Pulse duration, CLKR/X high or CLKR/X low
Setup time, external FSR high before CLKR low
Hold time, external FSR high after CLKR low
Setup time, DR valid before CLKR low
Hold time, DR valid after CLKR low
Setup time, external FSX high before CLKX low
Hold time, external FSX high after CLKX low
CLKR/X ext
CLKR/X ext
CLKR int
CLKR ext
CLKR int
CLKR ext
CLKR int
CLKR ext
CLKR int
CLKR ext
CLKX int
CLKX ext
CLKX int
CLKX ext
-7/-6/-5/-4
-L/-Q6/-Q5/-Q4
MIN
2P ^{(2) (3)}
P - 1 ⁽⁴⁾
14
4
6
4
14
4
3
3.5
14
4
6
3
MAX
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
(1) CLKRP = CLKXP = FSRP = FSXP = 0. If polarity of any of the signals is inverted, then the timing references of that signal are also
inverted.
(2) P = SYSCLK3 period in ns. For example, when running parts at 600 MHz, use P = 10 ns.
(3) Use whichever value is greater. Minimum CLKR/X cycle times must be met, even when CLKR/X is generated by an internal clock
source. The minimum CLKR/X cycle times are based on internal logic speed; the maximum usable speed may be lower due to EDMA
limitations and AC timing requirements.
(4) This parameter applies to the maximum McBSP frequency. Operate serial clocks (CLKR/X) in the reasonable range of 40/60 duty cycle.
200 Peripheral Information and Electrical Specifications
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