TMS320DM6435ZWT6 Datasheet, PDF (109/252 Pages) Texas Instruments – Digital Media Processor

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TMS320DM6435
Digital Media Processor
SPRS344C – NOVEMBER 2006 – REVISED JUNE 2008
3.7.3.11.3 EMIFA/VPSS Sub-Block 0 Configuration Choices
Table 3-40 through Table 3-42 show the configuration choices in the EMIFA/VPSS Sub-Block 0. For
instructions on how to use the different configuration choices tables for the EMIFA/VPSS Block and
Sub-Blocks, see Section 3.7.3.11.1. Note: italics in these tables indicate mandatory settings for a given
Minor Configuration option.
Before using Table 3-40 through Table 3-42 to configure the details of the EMIFA/VPSS Sub-Block 0, the
user should first select a Major Configuration Option for the EMIFA/VPSS Block (see Section 3.7.3.11.2).
After determining the Major Configuration Option (A, B, or E), the user can now use Table 3-40 through
Table 3-42 to refine Sub-Block 0 pin selections:
1. Go to the table with the Major Configuration Option chosen from Table 3-39.
2. Each Major Configuration Option is further divided down into multiple Minor Configuration Options.
Select a Minor Configuration Option that best suits the application need.
3. Within the chosen Minor Configuration Option, further refine the detailed pin configurations by selecting
the settings of PINMUX0 fields CCDCSEL, HVDSEL, CWENSEL, CFLDSEL, CI10SEL, CI32SEL,
CI54SEL, and CI76SEL.
4. The PINMUX Selection Fields columns show the settings needed to program the PINMUX0 register.
Table 3-40. EMIFA/VPSS Sub-Block 0 Configuration Choice A⁽¹⁾
MAJOR
CONFIG
OPTION
MINOR
CONFIG
OPTION
A1
A
A2
PINMUX SELECTION FIELDS
AEM AEAW
OTHERS
Cfg Summary
CCDCSEL = 0
HVDSEL = 0
CWENSEL = 0
000
000 CFLDSEL = 0
CI10SEL = 0
CI32SEL = 0
CI54SEL = 0
CI76SEL = 0
Cfg Summary
CCDCSEL = 1
HVDSEL = 0,1
CWENSEL = 0,1
000
000 CFLDSEL = 0,1
CI10SEL = 0,1
CI31SEL = 0,1
CI54SEL = 0,1
CI76SEL = 0,1
RESULTING PERIPHERALS/PINS
EMIFA
VPFE
# GPIO PINS
No EMIFA
-
No EMIFA
-
No CCDC
-
8-to-16-bit CCDC
1 = PCLK, YI[7:0]
1 = VD, HD
1 = C_WE
1 = C_FIELD
1 = CI[1:0]
1 = CI[3:2]
1 = CI[5:4]
1 = CI[7:6]
21 GP pins
0 = GP[54, 43:36]
0 = GP[53:52]
0 = GP[35]
0 = GP[34]
0 = GP[45:44]
0 = GP[47:46]
0 = GP[49:48]
0 = GP[51:50]
0-to-12 GP pins
-
0 = GP[53:52]
0 = GP[35]
0 = GP[34]
0 = GP[45:44]
0 = GP[47:46]
0 = GP[49:48]
0 = GP[51:50]
(1) Italics indicate mandatory settings for a given Minor Configuration option.
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Device Configuration 109