TMS320DM6435ZWT6 Datasheet, PDF (101/252 Pages) Texas Instruments – Digital Media Processor

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TMS320DM6435
Digital Media Processor
SPRS344C – NOVEMBER 2006 – REVISED JUNE 2008
As discussed in Section 3.7.3.2, Peripherals Spanning Multiple Pin Mux Blocks, the UART0 pins span
across two Pin Mux Blocks: UART0 Data Block, and UART0 Flow Control Block. For proper UART0
operation, the two pins in the UART0 Data Block must be configured for UART0 data functions. The two
pins in the UART0 Flow Control Block are optional.
Table 3-27 provides a different view of the UART0 Flow Control Block pin muxing, showing the UART0
Flow Control Block function based on PINMUX1.UR0FCBK setting. The selection options are also shown
pictorially in Figure 3-11.
PINMUX1.UR0FCBK
00
01
10
11
Table 3-27. UART0 Flow Control Block Function Selection
BLOCK FUNCTION
GPIO (2) (default)
UART0 Flow Control
PWM0 + GPIO (1)
Reserved
RESULTING PIN FUNCTIONS
GPIO: GP[88:87]
UART0: UCTS0, URTS0
PWM0: PWM0
GPIO: GP[87]
Reserved
In addition, the VDD3P3V_PWDN.UR0FC field determines the power state of the UART0 Flow Control
Block pins. The UART0 Flow Control Block pins default to powered down and not operational. To use
these pins, user must first program VDD3P3V_PWDN.UR0FC = 0 to power up the pins. For more details
on the VDD3P3V_PWDN.UR0FC field, see Section 3.2, Power Considerations.
The UART0 Flow Control Block features internal pullup resistors, which matches the UART inactive
polarity.
3.7.3.6 Timer0 Block
This block of 2 pins consists of Timer0, McBSP0, and GPIO muxed pins. The PINMUX1.TIM0BK register
field selects the pin functions in the Timer0 Block.
Table 3-28 summarizes the 2 pins in the Timer0 Block, the multiplexed function on each pin, and the
PINMUX configurations to select the corresponding function.
SIGNAL
NAME
TINP0L/
GP[98]
CLKS0/
TOUT0L/
GP[97]
Table 3-28. Timer0 Block Muxed Pins Selection
McBSP
FUNCTION
SELECT
MULTIPLEXED FUNCTIONS
Timer0
FUNCTION
SELECT
GPIO
FUNCTION
SELECT
–
CLKS0
–
TIM0BK = 11
TINP0L
TOUT0L
TIM0BK = 01/11
TIM0BK = 01
GP[98]
GP[97]
TIM0BK = 00
As discussed in Section 3.7.3.2, Peripherals Spanning Multiple Pin Mux Blocks, the McBSP0 pins span
across two Pin Mux Blocks: Serial Port Sub-Block0, and Timer0 Block. For proper McBSP0 operation, the
Serial Port Sub-Block0 must be programmed to select McBSP0 function. The McBSP0 CLKS0 pin in the
Timer0 Block is optional for McBSP0 operation. CLKS0 is only needed if you desire using CLKS0 as an
external clock source to the McBSP0 internal sample rate generator.
Table 3-29 provides a different view of the Timer0 Block pin muxing, showing the Timer0 Block function
based on PINMUX1.TIM0BK setting. The selection options are also shown pictorially in Figure 3-11.
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