TMS320DM6435ZWT6 Datasheet, PDF (203/252 Pages) Texas Instruments – Digital Media Processor

www.ti.com
TMS320DM6435
Digital Media Processor
SPRS344C – NOVEMBER 2006 – REVISED JUNE 2008
Table 6-53. Timing Requirements for McBSP as SPI Master or Slave: CLKSTP = 10b, CLKXP = 0⁽¹⁾⁽²⁾
(see Figure 6-31)
-7/-6/-5/-4
-L/-Q6/-Q5/-Q4
NO.
MASTER
SLAVE
UNIT
MIN
MAX
MIN
MAX
4
t_su(DRV-CKXL)
5
t_h(CKXL-DRV)
Setup time, DR valid before CLKX low
Hold time, DR valid after CLKX low
14
2 - 3P
ns
4
5 + 6P
ns
(1) P = SYSCLK3 period in ns. For example, when running parts at 600 MHz, use P = 10 ns.
(2) For all SPI Slave modes, the rate of the internal clock CLKG must be at least 8 times faster than that of the SPI data rate. User should
program sample rate generator to achieve maximum CLKG by setting CLKSM = CLKGDV = 1.
Table 6-54. Switching Characteristics Over Recommended Operating Conditions for McBSP as SPI
Master or Slave: CLKSTP = 10b, CLKXP = 0⁽¹⁾⁽²⁾ (see Figure 6-31)
NO.
PARAMETER
-7/-6/-5/-4
-L/-Q6/-Q5/-Q4
MASTER ⁽³⁾
SLAVE
UNIT
1
t_h(CKXL-FXL)
2
t_d(FXL-CKXH)
3
t_d(CKXH-DXV)
6
t_{dis(CKXL-DXHZ)}
Hold time, FSX low after CLKX low⁽⁴⁾
Delay time, FSX low to CLKX high⁽⁵⁾
Delay time, CLKX high to DX valid
Disable time, DX high impedance following
last data bit from CLKX low
MIN
T-4
L-4
-4
L-6
MAX
T + 5.5
L+4
5.5
L + 7.5
MIN
3P + 2.8
MAX
ns
ns
5P + 17 ns
ns
7
t_{dis(FXH-DXHZ)}
Disable time, DX high impedance following
last data bit from FSX high
P+3
3P + 17 ns
8
t_d(FXL-DXV)
Delay time, FSX low to DX valid
2P + 1.8
4P + 17 ns
(1) P = SYSCLK3 period in ns. For example, when running parts at 600 MHz, use P = 10 ns.
(2) For all SPI Slave modes, the rate of the internal clock CLKG must be at least 8 times faster than that of the SPI data rate. User should
program sample rate generator to achieve maximum CLKG by setting CLKSM = CLKGDV = 1.
(3) S = Sample rate generator input clock = 2P if CLKSM = 1 (P = SYSCLK3 period)
S = Sample rate generator input clock = 2P_clks if CLKSM = 0 (P_clks = CLKS period)
T = CLKX period = (1 + CLKGDV) * S
H = CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even
H = (CLKGDV + 1)/2 * S if CLKGDV is odd
L = CLKX low pulse width = (CLKGDV/2) * S if CLKGDV is even
L = (CLKGDV + 1)/2 * S if CLKGDV is odd
(4) FSRP = FSXP = 1. As a SPI Master, FSX is inverted to provide active-low slave-enable output. As a Slave, the active-low signal input
on FSX and FSR is inverted before being used internally.
CLKXM = FSXM = 1, CLKRM = FSRM = 0 for Master McBSP
CLKXM = CLKRM = FSXM = FSRM = 0 for Slave McBSP
(5) FSX should be low before the rising edge of clock to enable Slave devices and then begin a SPI transfer at the rising edge of the Master
clock (CLKX).
CLKX
FSX
DX
1
7
6
Bit 0
DR
Bit 0
2
8
4
Bit(n-1)
Bit(n-1)
3
(n-2)
5
(n-2)
(n-3)
(n-4)
(n-3)
(n-4)
Figure 6-31. McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 0
Submit Documentation Feedback
Peripheral Information and Electrical Specifications 203