TMS320DM6435ZWT6 Datasheet, PDF (165/252 Pages) Texas Instruments – Digital Media Processor

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TMS320DM6435
Digital Media Processor
SPRS344C – NOVEMBER 2006 – REVISED JUNE 2008
6.8 Interrupts
The C64x+ DSP interrupt controller combines device events into 12 prioritized interrupts. The source for
each of the 12 CPU interrupts is user programmable and is listed in Table 6-21. Also, the interrupt
controller controls the generation of the CPU exception and emulation interrupts. The NMI input to the
C64x+ DSP interrupt controller is not connected internally; therefore, the NMI interrupt is not available.
Table 6-22 summarizes the C64x+ interrupt controller registers and memory locations. For more details on
DSP interrupt controller, see the TMS320DM643x DMP DSP Subsystem Reference Guide (literature
number SPRU978).
DSP
SYSTEM
EVENT
NUMBER
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
ACRONYM
EVT0
EVT1
EVT2
EVT3
TINTL0
TINTH0
TINTL1
TINTH1
WDINT
EMU_DTDMA
EMU_RTDXRX
EMU_RTDXTX
IDMAINT0
IDMAINT1
VDINT0
VDINT1
VDINT2
HISTINT
H3AINT
PRVUINT
RSZINT
EDMA3CC_INTG
EDMA3CC_INT0
EDMA3CC_INT1
EDMA3CC_ERRINT
EDMA3TC_ERRINT0
EDMA3TC_ERRINT1
EDMA3TC_ERRINT2
PSCINT
Table 6-21. DM6435 DSP System Event Mapping
SOURCE
C64x+ Int Ctl 0
C64x+ Int Ctl 1
C64x+ Int Ctl 2
C64x+ Int Ctl 3
Timer 0 – TINT12
Timer 0 – TINT34
Timer 1 – TINT12
Timer 1 – TINT34
Timer 2 – TINT12
C64x+ EMC
Reserved
C64x+ RTDX
C64x+ RTDX
C64x+ EMC 0
C64x+ EMC 1
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
VPSS – CCDC 0
VPSS – CCDC 1
VPSS – CCDC 2
VPSS – Histogram
VPSS – AE/AWB/AF
VPSS – Previewer
VPSS – Resizer
Reserved
Reserved
Reserved
EDMACC Global Interupt
EDMACC Interrupt Region 0
EDMACC Interrupt Region 1
EDMA CC Error
EDMA TC0 Error
EDMA TC1 Error
EDMA TC2 Error
PSC ALLINT
Reserved
DSP
INTERRUPT
NUMBER
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
ACRONYM
GPIO0
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6
GPIO7
GPIOBNK0
GPIOBNK1
GPIOBNK2
GPIOBNK3
GPIOBNK4
GPIOBNK5
GPIOBNK6
PWM0
PWM1
PWM2
IICINT0
UARTINT0
UARTINT1
INTERR
EMC_IDMAERR
SOURCE
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
GPIO
Reserved
PWM0
PWM1
PWM2
I2C
UART0
UART1
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
C64x+ Interrupt Controller Dropped CPU
Interrupt Event
C64x+ EMC Invalid IDMA Parameters
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
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Peripheral Information and Electrical Specifications 165