TMS320DM6435ZWT6 Datasheet, PDF (185/252 Pages) Texas Instruments – Digital Media Processor

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PCLK
(Positive Edge Clocking)
TMS320DM6435
Digital Media Processor
SPRS344C – NOVEMBER 2006 – REVISED JUNE 2008
PCLK
(Negative Edge Clocking)
HD/VD
C_WE/C_FIELD
7, 9
11, 13
8, 10
12, 14
5
6
CCD[15:0]
Figure 6-20. VPFE (CCD) Slave Mode Input Data Timing
Table 6-37. Timing Requirements for VPFE (CCD) Master Mode⁽¹⁾ (see Figure 6-21)
-7/-6/-5/-4
NO.
-L/-Q6/-Q5/-Q4
UNIT
MIN
MAX
15
t_{su(CCDV-PCLK)}
16
t_h(PCLK-CCDV)
23
t_{su(CWEV-PCLK)}
24
t_h(PCLK-CWEV)
Setup time, CCD valid before PCLK edge
Hold time, CCD valid after PCLK edge
Setup time, C_WE valid before PCLK edge
Hold time, C_WE valid after PCLK edge
4.5
ns
1
ns
4.5
ns
1
ns
(1) The VPFE may be configured to operate in either positive or negative edge clocking mode. When in positive edge clocking mode the
rising edge of PCLK is referenced. When in negative edge clocking mode the falling edge of PCLK is referenced.
PCLK
(Positive Edge Clocking)
PCLK
(Positive Edge Clocking)
15
16
CCD[15:0]
23
24
C_WE/C_FIELD
Figure 6-21. VPFE (CCD) Master Mode Input Data Timing
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Peripheral Information and Electrical Specifications 185