TDA3MV_17 Datasheet, PDF (80/256 Pages) Texas Instruments – SoC for Advanced Driver Assistance Systems (ADAS) 15mm Package (ABF) Silicon Revision 2.0

TDA3MV, TDA3MA
TDA3LX, TDA3LA
SPRS964C – JUNE 2016 – REVISED JULY 2017
www.ti.com
(1) In a typical implementation, the power supply should target the NOM voltage.
(2) The voltage at the device ball should never be below the MIN voltage or above the MAX voltage for any amount of time. This
requirement includes dynamic voltage events such as AC ripple, voltage transients, voltage dips, etc.
(3) The DC voltage at the device ball should never be above the MAX DC voltage to avoid impact on device reliability and lifetime POH
(Power-On-Hours). The MAX DC voltage is defined as the highest allowed DC regulated voltage, without transients, seen at the ball.
(4) For all OPPs, AVS must be enabled to avoid impact on device reliability, lifetime POH (Power-On-Hours), and device power.
(5) The AVS voltages are device-dependent, voltage domain-dependent, and OPP-dependent. They must be read from the
STD_FUSE_OPP. For information about STD_FUSE_OPP Registers address, please refer to Control Module Section of the TRM.
The power supply should be adjustable over the following ranges for each required OPP:
– OPP_NOM: 0.85V - 1.06V
– OPP_OD: 0.94V - 1.15V
– OPP_HIGH: 1.05V - 1.25V
The AVS Voltages will be within the above specified ranges.
Table 5-8 describes the standard processor clocks speed characteristics vs OPP of the device.
Table 5-8. Supported OPP vs Max Frequency⁽²⁾
DESCRIPTION
OPP_NOM
OPP_OD
Max Freq. (MHz)
Max Freq. (MHz)
VD_DSPEVE
DSP_CLK
500
709
EVE_FCLK
500
667
VD_CORE
CORE_IPU1_CLK
212.8
N/A
ISS
212.8
N/A
L3_CLK
266
N/A
DDR3 / DDR3L
532 (DDR-1066)
N/A
DDR2
400 (DDR-800)
N/A
LPPDR2
333 (DDR-667)
N/A
ADC
20
N/A
(1) N/A in this table stands for Not Applicable.
(2) Maximum supported frequency is limited according to the Device Speed Grade (see Table 5-5).
OPP_HIGH
Max Freq. (MHz)
745
667
N/A
N/A
N/A
N/A
N/A
N/A
N/A
5.5.3 Maximum Supported Frequency
Device modules either receive their clock directly from an external clock input, directly from a PLL, or from
a PRCM. Table 5-9 lists the clock source options for each module on this device, along with the maximum
frequency that module can accept. To ensure proper module functionality, the device PLLs and dividers
must be programmed not to exceed the maximum frequencies listed in this table.
80
Specifications
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