TDA3MV_17 Datasheet, PDF (182/256 Pages) Texas Instruments – SoC for Advanced Driver Assistance Systems (ADAS) 15mm Package (ABF) Silicon Revision 2.0

TDA3MV, TDA3MA
TDA3LX, TDA3LA
SPRS964C – JUNE 2016 – REVISED JULY 2017
www.ti.com
Z=
ESR²
+ω^æçè EωSELSL
-
1
ωC
ö²
÷ø
where : w = 2π¦
SPRS91v_PCB_FREQ_02
Figure 8-7. Series Model Impedance Equation
Figure 8-8 shows the resonant frequency response of a typical capacitor with a self-resonant frequency of
55 MHz. The impedance of the capacitor is a combination of its series resistance and reactive capacitance
and inductance as shown in the equation above.
1.0e+01
S-Parameter Magnitude
Job: GCM155R71E153KA55_15NF;
1.0e+00
1.0e–01
1.0e–02
X_C=1/ωC
X_L=ωL
1.0e–03
Resonant frequency
(55 MHz) (minimum)
1.0e–04
1.00e–002
1.00e+000
1.00e+002
1.00e+004
Frequency (MHz)
1.00e+006
1.00e+008
SPRS91v_PCB_FREQ_03
Figure 8-8. Typical Impedance Profile of a Capacitor
Because a capacitor has series inductance and resistance that impacts its effectiveness, it is important
that the following recommendations are adopted in placing capacitors on the PDN.
Wherever possible, mount the capacitor with the geometry that minimizes the mounting inductance and
resistance. This was shown earlier in Figure 8-1. The capacitor mounting inductance and resistance
values include the inductance and resistance of the pads, trace, and vias. Whenever possible, use
footprints that have the lowest inductance configuration as shown in Figure 8-9
The length of a trace used to connect a capacitor has a big impact on parasitic inductance and resistance
of the mounting. This trace must be as short and as wide as possible. wherever possible, minimize
distance to supply and Gnd vias by locating vias nearby or within the capacitor’s solder pad landing.
Further improvements can be made to the mounting by placing vias to the side of capacitor lands or
doubling the number of vias as shown in Figure 8-9. If the PCB manufacturing processes allow it and if
cost-effective, via-in-pad (VIP) geometries are strongly recommended.
182 Applications, Implementation, and Layout
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