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TDA3MV_17 Datasheet, PDF (247/256 Pages) Texas Instruments – SoC for Advanced Driver Assistance Systems (ADAS) 15mm Package (ABF) Silicon Revision 2.0
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TDA3MV, TDA3MA
TDA3LX, TDA3LA
SPRS964C – JUNE 2016 – REVISED JULY 2017
Table 8-46 and Table 8-47 present the Static and Dynamic CVIDEO / SD-DAC TV analog composite
output specifications
Table 8-46. Static CVIDEO/SD-DAC Specifications
PARAMETER
Reference Current Setting Resistor
(RSET)
Output resistor between
cvideo_tvout and cvideo_vfb pins
(ROUT)
Load Resistor (RLOAD)
AC-Coupling Capacitor (Optional)
[CAC]
Total Capacitance from
cvideo_tvout to vssa_dac
Resolution
Integral Non-Linearity (INL), Best
Fit
Differential Non-Linearity (DNL)
Full-Scale Output Voltage
Full-Scale Output Current
Gain Error
Gain Mismatch (Luma-to-Chroma)
Output Impedance
TEST CONDITIONS
Normal Mode
TVOUT Bypass Mode
Normal Mode
TVOUT Bypass Mode
Normal Mode
TVOUT Bypass Mode
Normal Mode
TVOUT Bypass Mode
Normal Mode
TVOUT Bypass Mode
Normal Mode
TVOUT Bypass Mode
Normal Mode
TVOUT Bypass Mode
Normal Mode (RLOAD = 75 Ω)
TVOUT Bypass Mode (RLOAD =
1.5 kΩ)
Normal Mode
TVOUT Bypass Mode
Normal Mode (Composite) and
TVOUT Bypass Mode
Normal Mode (S-Video)
Normal Mode (Composite)
Normal Mode (S-Video)
Looking into cvideo_tvout nodes
MIN
4653
9900
2673
1485
220
-4
-1
-2.5
-1
N/A
-10
-20
-10
TYP
4700
10000
2700
MAX
4747
10100
2727
N/A
75-Ω Inside the Display
1500
1515
See External Amplifier Specification
300
N/A
10
4
1
2.5
1
1.3
0.7
470
10
20
N/A
10
75
UNIT
Ω
Ω
Ω
Ω
uF
pF
Bits
LSB
LSB
LSB
LSB
V
V
uA
%FS
%FS
%
Ω
Table 8-47. Dynamic CVIDEO/SD-DAC Specifications
PARAMETER
TEST CONDITIONS
MIN
Output Update Rate (FCLK)
Signal Bandwidth
3 dB
Spurious-Free Dynamic Range
(SFDR) within bandwidth
FCLK = 54 MHz, FOUT = 1 MHz
Signal-to-Noise Ration (SNR)
Power Supply Rejection (PSR)
FCLK = 54 MHz, FOUT = 1 MHz
Normal Mode, 100 mVpp @ 6
MHz on vdda_dac
TVOUT Bypass Mode, 100
mVpp @ 6 MHz on vdda_dac
TYP
54
6
50
54
6
20
MAX
60
UNIT
MHz
MHz
dBc
dB
dB
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Applications, Implementation, and Layout 247
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