TDA3MV_17 Datasheet, PDF (118/256 Pages) Texas Instruments – SoC for Advanced Driver Assistance Systems (ADAS) 15mm Package (ABF) Silicon Revision 2.0

TDA3MV, TDA3MA
TDA3LX, TDA3LA
SPRS964C – JUNE 2016 – REVISED JULY 2017
www.ti.com
SIGNALS
cpi_data13
cpi_data14
cpi_data15
cpi_wen
cpi_fid
cpi_hsync
cpi_vsync
cam_nreset
cam_strobe
cam_shutter
Table 7-6. Camera Parallel Interface (CPI) IOSETs (continued)
BALL
K18
K17
K19
K20
F21
F20
B18
C18
IOSET1
MUX
1
1
1
1
1
1
3
3
BALL
K18
K17
L21
K19
K20
F21
F20
W6
M17
M18
IOSET2
MUX
1
1
1
1
1
1
1
1
1
1
For more information, please contact your local TI representative.
7.7 External Memory Interface (EMIF)
The device has a dedicated interface to DDR3 and DDR3L SDRAM. It supports JEDEC standard
compliant DDR3 and DDR3L SDRAM devices with the following features:
• 16-bit or 32-bit data path to external SDRAM memory
• Memory device capacity: 128Mb, 256Mb, 512Mb, 1Gb, 2Gb, 4Gb and 8Gb devices (Single die only)
• One interface with associated DDR3/DDR3L PHYs
NOTE
For more information, see the EMIF Controller section of the Device TRM.
7.8 General-Purpose Memory Controller (GPMC)
The GPMC is the unified memory controller that interfaces external memory devices such as:
• Asynchronous SRAM-like memories and ASIC devices
• Asynchronous page mode and synchronous burst NOR flash
• NAND flash
NOTE
For more information, see the General-Purpose Memory Controller section of the Device
TRM.
7.8.1 GPMC/NOR Flash Interface Synchronous Timing
Table 7-7 and Table 7-8, Table 7-9 and Table 7-10 assume testing over the recommended operating
conditions and electrical characteristic conditions below (see Figure 7-4, Figure 7-5, Figure 7-6, Figure 7-
7, Figure 7-8 and Figure 7-9).
Table 7-7. GPMC/NOR Flash Interface Timing Requirements - Synchronous Mode - 1 Load
NO.
F12
F13
F21
F22
PARAMETER
t_su(dV-clkH)
t_h(clkH-dV)
t_{su(waitV-clkH)}
t_{h(clkH-waitV)}
DESCRIPTION
Setup time, read gpmc_ad[15:0] valid before gpmc_clk high
Hold time, read gpmc_ad[15:0] valid after gpmc_clk high
Setup time, gpmc_wait[1:0] valid before gpmc_clk high
Hold Time, gpmc_wait[1:0] valid after gpmc_clk high
MIN
MAX
UNIT
1.9
ns
1
ns
1.9
ns
1
ns
118 Timing Requirements and Switching Characteristics
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