TDA3MV_17 Datasheet, PDF (218/256 Pages) Texas Instruments – SoC for Advanced Driver Assistance Systems (ADAS) 15mm Package (ABF) Silicon Revision 2.0

TDA3MV, TDA3MA
TDA3LX, TDA3LA
SPRS964C – JUNE 2016 – REVISED JULY 2017
www.ti.com
8.8.2.2.5 DDR2 Keepout Region
The region of the PCB used for the DDR2 circuitry must be isolated from other signals. The DDR2
keepout region is defined for this purpose and is shown in Figure 8-41. The size of this region varies with
the placement and DDR routing. Additional clearances required for the keepout region are shown in
Table 8-26.
The region shown in Table 8-26 should encompass all the DDR2 circuitry and varies depending on
placement. Non-DDR2 signals should not be routed on the DDR signal layers within the DDR2 keepout
region. Non-DDR2 signals may be routed in the region, provided they are routed on layers separated from
DDR2 signal layers by a ground layer. No breaks should be allowed in the reference ground layers in this
region. In addition, the vdds_ddrx power plane should cover the entire keepout region. Routes for the two
DDR interfaces must be separated by at least 4x; the more separation, the better.
DDR2 Controller
A1
Device
Figure 8-41. DDR2 Keepout Region
PCB_DDR2_4
8.8.2.2.6 Bulk Bypass Capacitors
Bulk bypass capacitors are required for moderate speed bypassing of the DDR2 and other circuitry.
Table 8-27 contains the minimum numbers and capacitance required for the bulk bypass capacitors. Note
that this table only covers the bypass needs of the DDR2 interfaces and DDR2 device. Additional bulk
bypass capacitance may be needed for other circuitry.
Table 8-27. Bulk Bypass Capacitors
NO.
BC21
PARAMETER
vdds_ddrx bulk bypass capacitor (≥1µF) count⁽¹⁾
MIN
TYP
MAX
UNIT
10
Devices
BC22
vdds_ddrx bulk bypass total capacitance
50
μF
(1) These devices should be placed near the devices they are bypassing, but preference should be given to the placement of the high-
speed (HS) bypass capacitors and DDR2 signal routing.
8.8.2.2.7 High-Speed Bypass Capacitors
TI recommends that a PDN/power integrity analysis is performed to ensure that capacitor selection and
placement is optimal for a given implementation. This section provides guidelines that can serve as a
good starting point.
218 Applications, Implementation, and Layout
Copyright © 2016–2017, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: TDA3MV TDA3MA TDA3LX TDA3LA