TDA3MV_17 Datasheet, PDF (140/256 Pages) Texas Instruments – SoC for Advanced Driver Assistance Systems (ADAS) 15mm Package (ABF) Silicon Revision 2.0

TDA3MV, TDA3MA
TDA3LX, TDA3LA
SPRS964C – JUNE 2016 – REVISED JULY 2017
www.ti.com
Table 7-15 and Figure 7-20 assume testing over the recommended operating conditions and electrical
characteristic conditions below.
Table 7-15. Timing Requirements for I2C Input Timings⁽¹⁾
NO. PARAMETER
DESCRIPTION
1
t _c(SCL)
Cycle time, SCL
2
t _{su(SCLH-SDAL)}
Setup time, SCL high before SDA low (for a
repeated START condition)
3
t _h(SDAL-SCLL)
Hold time, SCL low after SDA low (for a START
and a repeated START condition)
4
t _w(SCLL)
Pulse duration, SCL low
5
t _w(SCLH)
Pulse duration, SCL high
6 t _{su(SDAV-SCLH)} Setup time, SDA valid before SCL high
7
t _h(SCLL-SDAV)
Hold time, SDA valid after SCL low
8
t _w(SDAH)
Pulse duration, SDA high between STOP and
START conditions
9
t _r(SDA)
Rise time, SDA
STANDARD MODE
MIN
MAX
10
4.7
4
4.7
4
250
0 ⁽³⁾
3.45 ⁽⁴⁾
4.7
1000
FAST MODE
MIN
MAX
2.5
0.6
0.6
1.3
0.6
100 ⁽²⁾
0 ⁽³⁾
1.3
20 + 0.1C _b
(5)
0.9 ⁽⁴⁾
300
UNIT
µs
µs
µs
µs
µs
ns
µs
µs
ns
10 t _r(SCL)
Rise time, SCL
1000
20 + 0.1C _b
(5)
300
ns
11 t _f(SDA)
Fall time, SDA
300
20 + 0.1C _b
(5)
300
ns
12 t _f(SCL)
Fall time, SCL
300
20 + 0.1C _b
(5)
300
ns
13 t _{su(SCLH-SDAH)}
Setup time, SCL high before SDA high (for
STOP condition)
4
0.6
µs
14 t _w(SP)
15 C _b ⁽⁵⁾
Pulse duration, spike (must be suppressed)
Capacitive load for each bus line
0
50
ns
400
400
pF
(1) The I2C pins SDA and SCL do not feature fail-safe I/O buffers. These pins could potentially draw current when the device is powered
down.
(2) A Fast-mode I²C-bus™ device can be used in a Standard-mode I²C-bus system, but the requirement t _su(SDA-SCLH)≥ 250 ns must then
be met. This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch
the LOW period of the SCL signal, it must output the next data bit to the SDA line t _r max + t_su(SDA-SCLH)= 1000 + 250 = 1250 ns
(according to the Standard-mode I²C-Bus Specification) before the SCL line is released.
(3) A device must internally provide a hold time of at least 300 ns for the SDA signal (referred to the V_IHmin of the SCL signal) to bridge the
undefined region of the falling edge of SCL.
(4) The maximum t_h(SDA-SCLL) has only to be met if the device does not stretch the low period [t_w(SCLL)] of the SCL signal.
(5) C_b = total capacitance of one bus line in pF. If mixed with HS-mode devices, faster fall-times are allowed.
140 Timing Requirements and Switching Characteristics
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