TCM29C23_12 Datasheet, PDF (8/20 Pages) Texas Instruments – VARIABLE-FREQUENCY PCM OR DSP INTERFACE

TCM29C23, TCM129C23
VARIABLE-FREQUENCY PCM OR DSP INTERFACE
SCTS029B − AUGUST 1989 − REVISED NOVEMBER 1996
receive filter transfer over recommended ranges of supply voltage and operating free-air
temperature (see Figure 2)
PARAMETER
Gain relative to gain at 1.02 kHz
TEST CONDITIONS
Below 200 Hz
200 Hz
300 Hz to 6 kHz
Input signal at PCM IN is 0 dBm0
6.6 kHz
6.8 kHz
8 kHz
9.2 kHz and above
MIN
−2
−1
− 0.5
−4
−6
MAX
0.5
0.5
0.5
0.3
0
−12
− 30
UNIT
dB
timing requirements
clock timing requirements over recommended ranges of supply voltage and operating free-air temperature
(see Figure 3)
t_c(CLK)
Clock period for CLKX, CLKR (2.048-MHz systems)
t_r, t_f
Rise and fall times for CLKX and CLKR
t_w(CLK)
Pulse duration for CLKX and CLKR (see Note 7)
t_w(DCLK) Pulse duration, DCLK (f_DCLK = 64 kHz to 2.048 MHz) (see Note 7)
Clock duty cycle, [t_w(CLK)/t_c(CLK)] for CLKX and CLKR
NOTE 7: FSX CLK must be phase locked with CLKX. FSR CLK must be phase locked with CLKR.
MIN
244
5
110
110
45%
NOM
50%
MAX
20
55%
UNIT
ns
ns
ns
ns
transmit timing requirements over recommended ranges of supply voltage and operating free-air
temperature, fixed-data-rate mode (see Figure 3)
t_d(FSX)
Frame-sync delay time
MIN
MAX
UNIT
60
t_c(CLK) − 60 ns
receive timing requirements over recommended ranges of supply voltages and operating free-air
temperature, fixed-data-rate mode (see Figure 4)
t_d(FSR)
Frame-sync delay time
MIN
MAX
UNIT
60
t_c(CLK)− 60 ns
transmit timing requirements over recommended ranges of supply voltage and operating free-air
temperature, variable-data-rate mode (see Figure 5)
t_d(TSDX)
t_d(FSX)
t_c(DCLKX)
Time-slot delay time from DCLKX
Frame-sync delay time
Clock period for DCLKX
MIN
MAX
UNIT
60 t_d(DCLKX)− 60 ns
60
t_c(CLK)− 60 ns
244
15620
ns
8
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