TCM29C23_12 Datasheet, PDF (13/20 Pages) Texas Instruments – VARIABLE-FREQUENCY PCM OR DSP INTERFACE

TCM29C23, TCM129C23
VARIABLE-FREQUENCY PCM OR DSP INTERFACE
SCTS029B − AUGUST 1989 − REVISED NOVEMBER 1996
PARAMETER MEASUREMENT INFORMATION
Time Slot 1
CLKX
t_d(FSX)
FSX
(nonsignaling
frames)
1
2
3
4
5
6
7
8
t_d(FSX)
t_r
t_f
t_w(CLK)
t_c(CLK)
Time Slot N
CLKX
t_pd1
PCM OUT
1
2
3
4
Bit 1^†
t_pd2
Bit 2
Bit 3
Bit 4
5
Bit 5
6
Bit 6
7
8
t_pd3
Bit 7
Bit 8^†
t_pd4
t_pd5
TSX
† _{Bit 1 = MSB = sign bit and locked in first on PCM IN or clocked out first on PCM OUT. Bit 8 = LSB = least significant bit and is clocked in}
last on PCM IN or is clocked out last on PCM OUT.
NOTE A: Inputs are driven from 0.45 V to 2.4 V. Time intervals are referenced to 2 V if the high level is indicated and 0.8 V if the low level
is indicated.
Figure 3. Transmit Timing (Fixed-Data Rate)
Time Slot 1
CLKR
t_d(FSR)
FSR
(nonsignaling
frames)
1
2
3
4
5
6
7
8
t_d(FSR) ^tr
t_f
t_w(CLK)
t_c(CLK)
Time Slot N
CLK
1
t_{su(PCM IN)}
PCM IN
Bit 1^†
Valid
2
3
t_{h(PCM IN)}
Bit 2
Valid
Bit 3
Valid
4
Bit 4
Valid
5
Bit 5
Valid
6
Bit 6
Valid
7
8
Bit 7
Valid
Bit 8^†
Valid
† _{Bit 1 = MSB = sign bit and locked in first on PCM IN or clocked out first on PCM OUT. Bit 8 = LSB = least significant bit and is clocked in last}
on PCM IN or is clocked out last on PCM OUT.
NOTE A: Inputs are driven from 0.45 V to 2.4 V. Time intervals are referenced to 2 V if the high level is indicated and 0.8 V if the low level
is indicated.
Figure 4. Receive Timing (Fixed-Data Rate)
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