TCM29C23_12 Datasheet, PDF (3/20 Pages) Texas Instruments – VARIABLE-FREQUENCY PCM OR DSP INTERFACE

TCM29C23, TCM129C23
VARIABLE-FREQUENCY PCM OR DSP INTERFACE
SCTS029B − AUGUST 1989 − REVISED NOVEMBER 1996
Terminal Functions
TERMINAL
NAME
I/O
NO.
DESCRIPTION
ANLG GND 16
Analog ground return for all internal voice circuits. ANLG GND is internally connected to DGTL GND.
ANLG IN + 17 I Noninverting analog input to uncommitted transmit operational amplifier.
ANLG IN − 18 I Inverting analog input to uncommitted transmit operational amplifier.
CLKR
11 I Receive master clock and data clock for the fixed-data-rate mode. Receive master clock only for variable-data-rate
mode. CLKR and CLKX are internally connected together.
CLKSEL
6 I Clock frequency selection. CLKSEL must be connected to V_BB, V_CC, or ground to reflect the master clock
frequency.
CLKX
11 I Transmit master clock and data clock for the fixed-data-rate mode. Transmit master clock only for
variable-data-rate mode. CLKR and CLKX are internally connected.
DCLKR
7 I Selects fixed- or variable-data-rate operation. When connected to V_BB, the device operates in the fixed-data-rate
mode. When DCLKR is not connected to V_BB, the device operates in the variable-data-rate mode and DCLKR
becomes the receive data clock, which operates at frequencies from 64 kHz to 4.096 MHz.
DGTL GND 10
Digital ground for all internal logic circuits. DGTL GND internally connected to ANLG GND.
FSR/TSRE
9 I Frame-synchronization clock input/time-slot enable for receive channel. In the fixed-data-rate mode, FSR
distinguishes between signaling and nonsignaling frames by a double- or single-length pulse, respectively. In the
variable-data-rate mode, this signal must remain high for the duration of the slot. The receive channel enters the
standby state when FSR is TTL low for 300 ms.
FSX/TSXE 12 I Frame-synchronization clock input/time-slot enable for the transmit channel. FSX/TSXE operates independently
of, but in an analogous manner to, FSR/TSRE. The transmit channel enters the standby state when FSX is low
for 300 ms.
GSR
4 I Input to the gain-setting network on the output power amplifier. Transmission level can be adjusted over a 12-dB
range depending upon the voltage at GSR.
GSX
19 O Output terminal of internal uncommitted operational amplifier. Internally, this is the voice-signal input to the transmit
filter.
PCM IN
8 I Receive PCM input. PCM data is clocked in on PCM IN on eight consecutive negative transition of the receive data
clock, which is CLKR in fixed-data-rate timing and DCLKR in variable-data-rate timing.
PCM OUT
13 O Transmit PCM output. PCM data is clocked out of PCM OUT on eight consecutive positive transition of the transmit
data clock, which is CLKX in fixed-data-rate timing and DCLKX in variable-data-rate timing.
PDN
5 I Power-down select. This device is inactive with a TTL low-level input to PDN and active with a TTL high-level input
to this terminal.
PWRO +
2 O Noninverting output of power amplifier. PWRO+ drives transformer hybrids or high-impedance loads directly in
either a differential or single-ended configuration.
PWRO −
3 O Inverting output of power amplifier. PWRO− is functionally identical to but complementary to PWRO +.
SIGX/ASEL 15
I A-law and μ-law operation select. When connected to V_BB, A-law is selected. When connected to V_CC or GND,
μ-law is selected.
TSX/DCLKX 12
I/O Transmit channel time-slot strobe (output) or data clock (input) for the transmit channel. In the fixed-data-rate mode,
TSX is an open-drain output to be used as an enable signal for a 3-state output buffer. In the variable-data-rate
mode, DCLKX becomes the transmit data clock, which operates at TTL levels from 64 kHz to 2.048 MHz.
V_BB
1
Most negative supply voltage. Input is − 5 V ± 5%.
V_CC
16
Most positive supply voltage. Input is 5 V ± 5%.
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