TCM29C23_12 Datasheet, PDF (18/20 Pages) Texas Instruments – VARIABLE-FREQUENCY PCM OR DSP INTERFACE

TCM29C23, TCM129C23
VARIABLE-FREQUENCY PCM OR DSP INTERFACE
SCTS029B − AUGUST 1989 − REVISED NOVEMBER 1996
PRINCIPLES OF OPERATION
conversion laws
The TCM29C23 and TCM129C23 provide pin-selectable A-law or μ-law operation as specified by the CCITT
G.711 recommendation. A-law operation is selected when ASEL is connected to V_BB. Signaling is not allowed
during A-law operation. μ-law operation is selected by connecting ASEL to V_CC or GND.
transmit operation
transmit filter
The input section provides gain adjustment in the pass band by means of an on-chip uncommitted operational
amplifier. The load impedance to ground (ANLG GND) at the amplifier output (GSX) must be greater than
10 kΩ in parallel with less than 50 pF. The input signal on ANLG IN+ can be either ac or dc coupled. The input
operational amplifier can also be used in the inverting mode or differential amplifier mode.
A low-pass antialiasing section is included on the device. This section provides 35-dB attenuation at the
sampling frequency. No external components are required to provide the necessary antialiasing function for the
switched-capacitor section of the transmit filter.
encoding
The encoder internally samples the output of the transmit filter and holds each sample on an internal sample-
and-hold capacitor. The encoder performs an analog-to-digital conversion on a switched-capacitor array. Digital
data representing the sample is transmitted on the first eight data clock bits of the next frame.
The autozero circuit corrects for dc offset on the input signal to the encoder using the sign bit averaging
technique. The sign bit from the encoder output is long-term averaged and subtracted from the input to the
encoder. All dc offset is removed from the encoder input waveform.
receive operation
decoding
The serial PCM word is received at PCM IN on the first eight data clock bits of the frame. Digital-to-analog
conversion is performed, and the corresponding analog sample is held on an internal sample-and-hold
capacitor. This sample is transferred to the receive filter.
receive filter
The receive section of the filter provides pass-band flatness and stop-band rejection that fulfills both the AT&T
D3/D4 specification and CCITT recommendation G.712. The filter contains the required compensation for the
(sin x)/x response of such decoders.
receive output power amplifiers
A balanced output amplifier allows maximum flexibility in output configuration. Either of the two outputs can be
used single ended (i.e., referenced to ANLG GND) to drive single-ended loads. Alternatively, the differential
output directly drives a bridged load. The output stage is capable of driving loads as low as
300 Ω single ended to a level of 12 dBm or 600 Ω differentially to a level of 15 dBm.
The receive channel transmission level may be adjusted between specified limits by manipulating of the GSR
input. GSR is internally connected to an analog gain-setting network. When GSR is connected to PWRO+, the
level is minimum. The output transmission level between 0 and −12 dB as GSR is adjusted (with an adjustable
resistor) between PWRO + and PWRO −.
Transmission levels are specified relative to the receive channel output under digital milliwatt conditions
(i.e., when the digital input at PCM IN is the eight-code sequence specified in CCITT recommendation G.711).
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