TCM29C23_12 Datasheet, PDF (19/20 Pages) Texas Instruments – VARIABLE-FREQUENCY PCM OR DSP INTERFACE

TCM29C23, TCM129C23
VARIABLE-FREQUENCY PCM OR DSP INTERFACE
SCTS029B − AUGUST 1989 − REVISED NOVEMBER 1996
APPLICATION INFORMATION
output gain-set design considerations (see Figure 8)
PWRO+ and PWRO− are low-impedance complementary outputs. The voltages at the nodes are:
V_{O +} at PWRO +
V_{O −} at PWRO −
V_O = V_{O +} − V_{O −} (total differential response)
R1 and R2 are a gain-setting resistor network with the center tap to the GSR input.
A value greater than 10 kΩ and less than 100 kΩ for R1 + R2 is recommended because of the following:
The parallel combination of R1 + R2 and R_L sets the total loading.
The total capacitance at the GSR input and the parallel combination of R1 and R2 define a time constant
that has to be minimized to avoid inaccuracies.
V_AD represents the maximum available digital milliwatt output response (V_A = 3.06 V rms).
V_OD = A • V_AD
1 + (R1/R2)
where A = _{4 + (R1/R2)}
V_{O +}
R1
R_L
V_OD
2
PWRO+
TCM19C23
4 _GSR TCM129C23
R2
3
PWRO−
V_{O −}
Figure 8. Gain-Setting Configuration
8
PCM IN
Digital Milliwatt Sequence
Per CCITT G. 711
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