TCM29C23_12 Datasheet, PDF (17/20 Pages) Texas Instruments – VARIABLE-FREQUENCY PCM OR DSP INTERFACE

TCM29C23, TCM129C23
VARIABLE-FREQUENCY PCM OR DSP INTERFACE
SCTS029B − AUGUST 1989 − REVISED NOVEMBER 1996
PRINCIPLES OF OPERATION
fixed-data-rate timing
Fixed-data-rate timing is selected by connecting DCLKR to V_BB. It uses master clocks CLKX and CLKR, frame-
synchronizer clocks FSX and FSR, and output TSX. FSX and FSR are inputs that set the sampling frequency.
Data is transmitted on PCM OUT on the first eight positive transitions of CLKX following the rising edge of FSX.
Data is received on PCM IN on the first eight falling edges of CLKR following FSX. A digital-to-analog (D/A)
conversion is performed on the received digital word and the resulting analog sample is held on an internal
sample-and-hold capacitor until transferred to the receive filter.
variable-data-rate timing
Variable-data-rate timing is selected by connecting DCLKR to the bit clock for the receive PCM highway rather
than to V_BB. It uses master clocks CLKX and CLKR, bit clocks DCLKX and DCLKR, and frame-synchronization
clocks FSX and FSR.
Variable-data-rate timing allows for a flexible data frequency. The frequency of the bit clocks can be varied from
64 kHz to 4.096 MHz. The bit clocks must be asynchronous.
When the FSX/TSXE input is high, PCM data is transmitted from PCM OUT onto the highway on the next eight
consecutive positive transitions of DCLKX. Similarly, while the FSR/TSRE input is high, the PCM word is
received from the highway by PCM IN on the next eight consecutive negative transitions of DCLKR.
The transmitted PCM word is in all remaining time slots in the frame as long as DCLKX is pulsed and FSX is
held high. This feature, which allows the PCM word to be transmitted to the PCM highway more than once per
frame if desired, is available only with variable-data-rate timing. Signaling is allowed only in the fixed-data-rate
mode because the variable-data-rate mode provides no means with which to specify a signaling frame.
asynchronous operation
To avoid crosstalk problems associated with special interrupt circuits, the design includes separate
digital-to-analog converters and voltage references on the transmit and receive sides to allow completely
independent operation of the two channels. In either timing mode, the master clock, data clock, and time-slot
strobe must be synchronized at the beginning of each frame. Specifically, in the variable-rate mode, the falling
edge of CLKX must occur within t_d(FSX) ns after the rise of FSX and the falling edge of DCLKX must occur within
t_TSDX ns after the rise of FSX. CLKX and DCLKX are synchronized once per frame but may be of different
frequencies. The receive channel operates in a similar manner and is completely independent of the transmit
timing (see Figure 6). This approach requires the provision of two separate master clocks but avoids the use
of a synchronizer, which can cause intermittent data conversion errors.
precision voltage references
Voltage references that determine the gain and dynamic range characteristics of the device are generated
internally. No external components are required to provide the voltage references. A difference in subsurface
charge density between two suitably implanted MOS devices is used to derive a temperature- and bias-stable
reference voltage, which are calibrated during the manufacturing process. Separate references are supplied
to the transmit and receive sections, and each is calibrated independently. Each reference value is then further
trimmed in the gain-setting operational amplifiers to a final precision value. Manufacturing tolerances of typically
± 0.04 dB in absolute gain can be achieved for each half channel, providing the user a significant margin to
compensate for error in other system components.
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