DS90C3201_14 Datasheet, PDF (8/23 Pages) Texas Instruments – 3.3V 8 MHz to 135 MHz Dual FPD-Link Transmitter

DS90C3201
SNLS192D – APRIL 2005 – REVISED APRIL 2013
AC Timing Diagrams (continued)
250
Incr. Pattern
(max)
200 ^{Worst Case}
(max)
150
100
50
0
0
Worst Case
(typ)
Incr. Pattern
(typ)
20 40 60 80 100 120 140 160
FREQUENCY (MHz)
Figure 6. Typical and Max ICC with Worst Case and Incremental Test Pattern
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Figure 7. LVDS Transition Times
80%
80%
20%
TCIT
20%
TCIT
Figure 8. Input Clock Transition Time
TCIP
TCIH
TCIL
TxCLK IN V_DD/2
V_DD/2
TSTC
THTC
TxIN [69:0] _VDD/2
V_DD/2
TxCLK OUT-
TxCLK OUT+
TCCD
0V
Figure 9. Input Setup/Hold Time, High/Low Time, and Clock In to Clock Out Latency
8
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