DS90C3201_14 Datasheet, PDF (18/23 Pages) Texas Instruments – 3.3V 8 MHz to 135 MHz Dual FPD-Link Transmitter

DS90C3201
SNLS192D – APRIL 2005 – REVISED APRIL 2013
Address
28d/1ch
29d/1dh
30d/1eh
31d/1fh
Table 1. DS90C3201 Two-Wire Serial Interface Register Table (continued)
R/W
RESET
R/W
PWDN
R/W
PWDN
R/W
PWDN
R/W
PWDN
Bit #
[7]
[6]
[5]
[4]
[3:2]
[1:0]
[7:5]
[4]
[3]
[2]
[1]
[0]
[7:5]
[4]
[3]
[2]
[1]
[0]
[7:6]
[5]
[0:4]
Description
Vod adjustment for TCLK channel
0: TCLK Vod is the same as TXE EVEN BANK (Default)
1: TCLK Vod is the same as TXO ODD BANK
Vos adjustment for TCLK channel
0: TCLK Vos is the same as TXE EVEN BANK (Default)
1: TCLK Vos is the same as TXO ODD BANK
Vod adjustment for TXE EVEN BANK
0: Vod set at 400mV ( Default)
1: Vod set at 250mv
Vod adjustment for TXO ODD BANK
0: Vod set at 400mV ( Default)
1: Vod set at 250mv
Vos adjustment for TXE EVEN BANK
11: NA
10: LVDS DR O/P Vos set at 0.8V
01: LVDS DR O/P Vos set at 1.0V
00: LVDS DR O/P Vos set at 1.2V (Default)
Vos adjustment for TXO ODD BANK
11: NA
10: LVDS DR O/P Vos set at 0.8V
01: LVDS DR O/P Vos set at 1.0V
00: LVDS DR O/P Vos set at 1.2V (Default)
Reserved
I/O disable control for TXE EVEN BANK channel E,
1: Disable, 0: Enable (Default)
I/O disable control for TXE EVEN BANK channel D,
1: Disable, 0: Enable (Default)
I/O disable control for TXE EVEN BANK channel C,
1: Disable, 0: Enable (Default)
I/O disable control for TXE EVEN BANK channel B,
1: Disable, 0: Enable (Default)
I/O disable control for TXE EVEN BANK channel A,
1: Disable, 0: Enable (Default)
Reserved
I/O disable control for TXO ODD BANK channel E,
1: Disable, 0: Enable (Default)
I/O disable control for TXO ODD BANK channel D,
1: Disable, 0: Enable (Default)
I/O disable control for TXO ODD BANK channel C,
1: Disable, 0: Enable (Default)
I/O disable control for TXO ODD BANK channel B,
1 Disable, 0: Enable (Default)
I/O disable control for TXO ODD BANK channel A,
1: Disable, 0: Enable (Default)
11: LVDS O/Ps available as long as "NO CLK" is at HIGH
regardless PLL lock or not
10: LVDS O/Ps available after 1K of TCLK cycles detected
& PLL generated strobes are within 0.5UI respect to
REFCLK
01: LVDS O/Ps available after 2K of TCLK cycles detected
00: Default ; LVDS O/Ps available after 1K of TCLK cycles
detected
0: Default; to select the size of wait counter between 1K or
2K, Default is 1K
Reserved
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Default Value
0000_0000
0000_0000
0000_0000
0000_0000
18
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