DS90C3201_14 Datasheet, PDF (6/23 Pages) Texas Instruments – 3.3V 8 MHz to 135 MHz Dual FPD-Link Transmitter

DS90C3201
SNLS192D – APRIL 2005 – REVISED APRIL 2013
Transmitter Switching Characteristics (continued)
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
Parameter
Min
TPPos3
Transmitter Output Pulse Position for bit 3 (6th bit) (Figure 15)
5 UI − 0.2
TPPos2
Transmitter Output Pulse Position for bit 2 (7th bit) (Figure 15)
6 UI − 0.2
TSTC
Required TxIN Setup to TCLK IN (Figure 9)
1.5
Register addr 26d/19h bit [2:0] = 000b (Default)
THTC
Required TxIN Hold to TCLK IN (Figure 9)
1.5
Register addr 26d/19h bit [2:0] = 000b (Default)
TSTC/THTC
Programmable
adjustment
Register addr 26d/19h bit [2:0] = 001b (Figure 14)
Decrease TSTC ~400ps from Default;
Increase THTC ~400ps from Default
Register addr 26d/19h bit [2:0] = 010b,
Decrease TSTC ~800ps from default;
Increase THTC ~800ps from Default
Register addr 26d/19h bit [2:0] = 011b,
Decrease TSTC ~1200ps from Default;
Increase THTC ~1200ps from Default
Register addr 26d/19h bit [2:0] = 111b,
Increase TSTC ~800ps from Default;
Decrease THTC ~800ps from Default
Register addr 26d/19h bit [2:0] = 110b,
Increase TSTC ~600ps from Default;
Decrease THTC ~600ps from Default
Register addr 26d/19h bit [2:0] = 101b,
Increase TSTC ~400ps from Default;
Decrease THTC ~400ps from Default
Register addr 26d/19h bit [2:0] = 100b,
Increase TSTC ~200ps from Default;
Decrease THTC ~200ps from Default
TCCD
Transmitter TCLKIN (LVTTL) to CLKOUT f = 135 MHz
10
(LVDS) Latency
(Figure 9) ⁽²⁾
f = 85 MHz ⁽³⁾
20
f = 65 MHz ⁽³⁾
25
f = 40 MHz ⁽³⁾
40
f = 25 MHz ⁽³⁾
60
f = 8 MHz
180
TPPLS
Transmitter Phase Lock Loop Set (Figure 10)
TPDD
Transmitter Powerdown Delay (Figure 11)
(2) The typical transmitter TCCD latency is: 1.786*T + 4.19 ns – 2 UI, where T = TCLK IN period.
(3) Specification is ensured by characterization.
Typ
5
6
0.69
0.70
0.5/
1.0
0/
1.5
-0.5/
2.0
1.5/
0
1.4/
0
1.1/
0.3
0.9/
0.5
www.ti.com
Max
5 UI + 0.2
6 UI + 0.2
Unit
UI ⁽¹⁾
UI ⁽¹⁾
ns
ns
ns
ns
ns
ns
ns
ns
ns
20
ns
30
ns
40
ns
50
ns
70
ns
200
ns
10
ms
100
ns
Two-Wire Serial Communication Interface
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
f_SC
S2CLK Clock Frequency
SC:LOW
Clock Low Period
R_P = 4.7KΩ, C_L = 50pF
1.5
SC:HIGH
Clock High Period
R_P = 4.7KΩ, C_L = 50pF
0.6
SCD:TR
S2CLK and S2DAT Rise Time
R_P = 4.7KΩ, C_L = 50pF
SCD:TF
S2CLK and S2DAT Fall Time
R_P = 4.7KΩ, C_L = 50pF
SU:STA
Start Condition Setup Time
R_P = 4.7KΩ, C_L = 50pF
0.6
HD:STA
Start Condition Hold Time
R_P = 4.7KΩ, C_L = 50pF
0.6
HD:STO
Stop Condition Hold Time
R_P = 4.7KΩ, C_L = 50pF
0.6
SC:SD
Clock Falling Edge to Data
R_P = 4.7KΩ, C_L = 50pF
0
SD:SC
Data to Clock Rising Edge
R_P = 4.7KΩ, C_L = 50pF
0.1
SCL:SD
S2CLK Low to S2DAT Data Valid
R_P = 4.7KΩ, C_L = 50pF
0.1
400
kHz
us
us
0.3
us
0.3
us
us
us
us
us
us
0.9
us
6
Submit Documentation Feedback
Product Folder Links: DS90C3201
Copyright © 2005–2013, Texas Instruments Incorporated