DS90C3201_14 Datasheet, PDF (5/23 Pages) Texas Instruments – 3.3V 8 MHz to 135 MHz Dual FPD-Link Transmitter

DS90C3201
www.ti.com
SNLS192D – APRIL 2005 – REVISED APRIL 2013
Electrical Characteristics ^{(1) (2) (3)} (continued)
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
V_OS
Offset Voltage (Programmable
R_L = 100Ω, Register addr 28d/1ch
register)
bit [3:2] (TXE) = 00b,
bit [1:0] (TXO) = 00b, (Default)
1.0
1.2
1.5
V
R_L = 100Ω, Register addr 28d/1ch
bit [3:2] (TXE) = 01b,
bit [1:0] (TXO) = 01b
0.8
1.0
1.2
V
R_L = 100Ω, Register addr 28d/1ch
bit [3:2] (TXE) = 10b,
bit [1:0] (TXO) = 10b
0.6
0.8
1.0
V
ΔV_OS
Change in V_OS between
complimentary output states
50
mV
I_OS
Output Short Circuit Current
TRANSMITTER SUPPLY CURRENT
V_OUT = 0V
−50
mA
ICCTW
Transmitter Supply Current, Worst
Case
(Figure 4, Figure 6) ⁽⁴⁾
R_L = 100Ω,
C_L = 5pF,
Worst Case Pattern,
Default Register
Settings
f = 8 MHz
f = 135 MHz
20
60
95
mA
65
150
235
mA
ICCTG
Transmitter Supply Current,
Incremental Test Pattern
(Figure 5 Figure 6) ⁽⁵⁾
R_L = 100Ω,
C_L = 5pF,
Worst Case Pattern,
Default Register
Settings
f = 8 MHz
f = 135 MHz
15
55
90
mA
40
110
175
mA
ICCTZ
Transmitter Supply Current, Power
Down
PDWNB = Low,
R_L = 100Ω, C_L = 5pF,
Default Register Settings
2
mA
(4) The worst case test pattern produces a maximum toggling of digital circuits, LVDS I/O and LVCMOS/LVTTL I/O.
(5) The incremental test pattern tests device power consumption for a “typical” LCD display pattern.
Recommended Transmitter Input Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
T_CIT
T_CIP
T_CIH
T_CIL
T_XIT
TJIT_RMS
Parameter
TCLK IN Transition Time (Figure 8)
TCLK IN Period (Figure 9)
TCLK IN High Time (Figure 9)
TCLK IN Low Time (Figure 9)
TxIN Transition Time
TCLK IN Jitter (RMS)
Min
7.4
0.30T_CIP
0.30T_CIP
(1)
Typ
T
0.50T_CIP
0.50T_CIP
±200
Max
(1)
125.0
0.70T_CIP
0.70T_CIP
(1)
Unit
ns
ns
ns
ns
ns
ps
(1) Less than 5ns or 30% of TCIP, whichever is less.
Transmitter Switching Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
Parameter
Min
Typ
Max
Unit
LLHT
LVDS Low-to-High Transition Time (Figure 7)
0.6
1.5
ns
LHLT
TPPos1
TPPos0
TPPos6
TPPos5
TPPos4
LVDS High-to-Low Transition Time (Figure 7)
Transmitter Output Pulse Position for bit 1 (1st bit) (Figure 15)
Transmitter Output Pulse Position for bit 0 (2nd bit) (Figure 15)
Transmitter Output Pulse Position for bit 6 (3rd bit) (Figure 15)
Transmitter Output Pulse Position for bit 5 (4th bit) (Figure 15)
Transmitter Output Pulse Position for bit 4 (5th bit) (Figure 15)
0.6
1.5
ns
−0.2
0
+0.2
UI ⁽¹⁾
1 UI − 0.2
1
1 UI + 0.2
UI ⁽¹⁾
2 UI − 0.2
2
2 UI + 0.2
UI ⁽¹⁾
3 UI − 0.2
3
3 UI + 0.2
UI ⁽¹⁾
4 UI − 0.2
4
4 UI + 0.2
UI ⁽¹⁾
(1) A Unit Interval (UI) is defined as 1/7th of an ideal clock period (TCIP/7). E.g. For an 11.76ns clock period (85MHz), 1 UI = 1.68ns
(Figure 13)
Copyright © 2005–2013, Texas Instruments Incorporated
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