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| DS90C3201_14 Datasheet, PDF (11/23 Pages) Texas Instruments – 3.3V 8 MHz to 135 MHz Dual FPD-Link Transmitter | |||
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www.ti.com
DS90C3201
SNLS192D â APRIL 2005 â REVISED APRIL 2013
AC Timing Diagrams (continued)
TCLK OUT
(Differential)
TXOA+/-
VDIFF = 0V
Previous
cycle
Current
Cycle
VDIFF = 0V
OA1-1 OA0-1 OA6
OA5
OA4
OA3
OA2
OA1
OA0
Next
cycle
TXOB+/-
OB1-1 OB0-1 OB6
OB5
OB4
OB3
OB2
OB1
OB0
TXOC+/-
OC1-1 OC0-1 OC6
OC5
OC4
OC3
OC2
OC1
OC0
TXOD+/-
OD1-1 OD0-1 OD6
OD5
OD4
OD3
OD2
OD1
OD0
TXOE+/-
OE1-1 OE0-1 OE6
OE5
OE4
OE3
OE2
OE1
OE0
TXEA+/-
EA1-1 EA0-1 EA6
EA5
EA4
EA3
EA2
EA1
EA0
TXEB+/-
EB1-1 EB0-1 EB6
EB5
EB4
EB3
EB2
EB1
EB0
TXEC+/-
EC1-1 EC0-1 EC6
EC5
EC4
EC3
EC2
EC1
EC0
TXED+/-
ED1-1 ED0-1 ED6
ED5
ED4
ED3
ED2
ED1
ED0
TXEE+/-
EE1-1 EE0-1 EE6
EE5
EE4
EE3
EE2
EE1
EE0
TPPos1
TPPos0
TPPos6
TPPos5
TPPos4
TPPos3
TPPos2
(1 UI)
(2 UI)
(3 UI)
(4 UI)
(5 UI)
(6 UI)
(7 UI)
Figure 15. LVDS Input Mapping and Ideal Transmitter Pulse Position
Copyright © 2005â2013, Texas Instruments Incorporated
Product Folder Links: DS90C3201
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