DS90C185_13 Datasheet, PDF (8/22 Pages) Texas Instruments – Low Power 1.8V FPD-Link (LVDS) Serializer

DS90C185
SNLS402D – FEBRUARY 2012 – REVISED FEBRUARY 2013
AC Timing Diagrams
T
CLK
Dx,
x = ODD
Dx,
x = EVEN
Falling Edge CLK (RFB = GND) shown
NOTE: The worst case test pattern produces a maximum toggling of digital circuits, LVDS I/O and LVCMOS I/O.
Figure 1. “Worst Case” Test Pattern
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Signal
Signal Pattern
Signal Frequency
PCLK
f
R0
f / 16
R1
f/8
R2
f/4
R3
f/2
R4
Steady State, Low
R5
Steady State, Low
G0
f / 16
G1
f/8
G2
f/4
G3
f/2
G4
Steady State, Low
G5
Steady State, Low
B0
f / 16
B1
f/8
B2
f/4
B3
f/2
B4
Steady State, Low
B5
Steady State, Low
HS
Steady State, High
VS
Steady State, High
DE
Steady State, High
NOTE: Recommended pin to signal mapping for 18 bits per pixel, customer may choose to define differently. The 16
grayscale test pattern tests device power consumption for a “typical” LCD display pattern. The test pattern
approximates signal switching needed to produce groups of 16 vertical stripes across the display.
NOTE: Figure 1 and Figure 2 show a falling edge data strobe (CLK).
Figure 2. “16 Grayscale” Test Pattern - DS90C185
Figure 3. DS90C185 (Transmitter) LVDS Output Load
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