DS90C185_13 Datasheet, PDF (11/22 Pages) Texas Instruments – Low Power 1.8V FPD-Link (LVDS) Serializer

DS90C185
www.ti.com
SNLS402D – FEBRUARY 2012 – REVISED FEBRUARY 2013
LVDS INTERFACE, TFT COLOR DATA RECOMMENDED MAPPING
Different color mapping options exist. Check with the color mapping of the Deserializer / TCON device that is
used to ensure compatible mapping for the application. The DS90C185 supports single pixel interfaces with
either 24bpp or 18bpp color depths.
The DS90C185 provides four LVDS data lines along with an LVDS clock line (4D+C) for the 28 LVCMOS data
inputs. The 28 bit interface typically assigns 24 bits to RGB color data, 3 bits to video control (HS, VS and DE)
and one spare bit can be ignored, used for L/R signaling or function as a general purpose bit. The single pixel
24bpp 4D+C LVDS interface mapping is shown Figure 13. A single pixel 18bpp mode is also supported by
utilizing the 18B_MODE pin. In this configuration the TxOUT3 output channel is place in TRI-STATE® to save
power. Its respective inputs are ignored. This mapping is shown in Figure 12.
TxCLKOUT+/-
(Diff)
TxOUT3+/-
(SE)
TxOUT2+/-
(SE)
TxOUT1+/-
(SE)
TxOUT0+/-
(SE)
Current Cycle
TRI-STATE
D20 D19 D18 D17 D16 D15 D14
D13 D12 D11 D10 D9 D8 D7
D6 D5 D4 D3 D2 D1 D0
Figure 12. DS90C185 LVDS Map — 18B_MODE = H
TxCLKOUT+/-
(Diff)
TxOUT3+/-
(SE)
TxOUT2+/-
(SE)
TxOUT1+/-
(SE)
TxOUT0+/-
(SE)
Current Cycle
D27 D26 D25 D24 D23 D22 D21
D20 D19 D18 D17 D16 D15 D14
D13 D12 D11 D10 D9 D8 D7
D6 D5 D4 D3 D2 D1 D0
Figure 13. DS90C185 LVDS Map — 18B_MODE = L
COLOR MAPPING INFORMATION
A defacto color mapping is shown next. Different color mapping options exist. Check with the color mapping of
the Deserializer / TCON device that is used to ensure compatible mapping for the application.
Table 2. 24bpp / MSB on CH3
DS90C187 Input
D22
D21
D5
D4
D3
D2
D1
D0
Color Mapping
R7
R6
R5
R4
R3
R2
R1
R0
Note
MSB
LSB
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