DS90C185_13 Datasheet, PDF (14/22 Pages) Texas Instruments – Low Power 1.8V FPD-Link (LVDS) Serializer

DS90C185
SNLS402D – FEBRUARY 2012 – REVISED FEBRUARY 2013
Table 5. Pixel Clock Edge
RFB
0
1
Result
FALLING edge
RISING edge
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Power Management
The DS90C185 has several features to assist with managing power consumption. The 18B_MODE pin allows the
DS90C185 to power down the unused LVDS driver for RGB-666 (18 bit color) applications. If no clock is applied
to the CLK pin, the DS90C185 will enter a low power state. To place the DS90C185 in its lowest power state, the
device can be powered down by driving the PDB pin to LOW.
Sleep Mode (PDB)
The DS90C185 provides a power down feature. When the device has been powered down, current draw through
the supply pins is minimized and the PLL is shut down. The LVDS drivers are also powered down with their
outputs pulled to GND through 100Ω resistors.
Table 6. Power Down Select
PDB
0
1
Result
SLEEP Mode (default)
ACTIVE (enabled)
LVDS Outputs
The DS90C185's LVDS drivers are compatible with ANSI/TIA/EIA-644–A LVDS receivers. The LVDS drivers an
output a power saving low V_OD or a higher V_OD to enable longer trace and cable lengths by configuring the
VODSEL pin.
VODSEL
0
1
Table 7. VOD Select
Result
±180 mV (360mVpp)
±300 mV (600mVpp)
For more information regarding the electrical characteristics of the LVDS outputs, refer to the LVDS DC
Characteristics and LVDS Switching Specifications.
18 bit / 24 bit Color Mode (18B)
The 18B pin can be used to further save power by powering down the 4th LVDS driver in each used bank when
the application requires only 18 bit color or 3D+C LVDS. Set the 18B pin to logic HIGH to TRI-STATE® TxOUT3
+/-. For 24 bit color applications this pin should be set to logic LOW. Note that the power down function takes
priority over the TRI-STATE® function.
Table 8. Color Depth Configurations
18B_Mode
0
1
Result
24bpp, LVDS 4D+C
18bpp, LVDS 3D+C
LVCMOS Inputs
The DS90C185 has 28 data inputs. These inputs are typically used for 24 or 18 bits of RGB video with 1, 2 or 3
video control signal (HS, VS and DE) inputs and one spare bit that can be used for L/R signaling or function as a
general purpose bit. All LVCMOS input pins are designed for 1.8V LVCMOS logic. All LVCMOS inputs, including
clock, data and configuration pins have an internal pull down resistor to set a default state. If any LVCMOS
inputs are unused, they can be left as no connect (NC) or connected to ground.
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