DS90C185_13 Datasheet, PDF (15/22 Pages) Texas Instruments – Low Power 1.8V FPD-Link (LVDS) Serializer

DS90C185
www.ti.com
SNLS402D – FEBRUARY 2012 – REVISED FEBRUARY 2013
APPLICATIONS INFORMATION
Power Up Sequence
The V_DD power supply pins do not require a specific power on sequence and can be powered on in any order.
However, the PDB pin should only be set to logic HIGH once the power sent to all supply pins is stable. Active
clock and data inputs should not be applied to the DS90C185 until all of the input power pins have been powered
on, settled to the recommended operating voltage and the PDB pin has be set to logic HIGH.
The user experience can be impacted by the way a system powers up and powers down an LCD screen. The
following sequence is recommended:
Power up sequence (DS90C185 PDB input initially LOW):
1. Ramp up LCD power (maybe 0.5ms to 10ms) but keep backlight turned off.
2. Wait for additional 0-200ms to ensure display noise won’t occur.
3. Toggle DS90C185 power down pin to PDB = V_IH.
4. Enable video source output; start sending black video data.
5. Send >1ms of black video data; this allows the DS90C185 to be phase locked, and the display to show black
data first.
6. Start sending true image data.
7. Enable backlight.
Power Down sequence (DS90C185 PDB input initially HIGH):
1. Disable LCD backlight; wait for the minimum time specified in the LCD data sheet for the backlight to go low.
2. Video source output data switch from active video data to black image data (all visible pixel turn black); drive
this for >2 frame times.
3. Set DS90C185 power down pin to PDB = GND.
4. Disable the video output of the video source.
5. Remove power from the LCD panel for lowest system power.
Power Supply Filtering
The DS90C185 has several power supply pins at 1.8V. It is important that these pins all be connected and
properly bypassed. Bypassing should consist of at least one 0.1µF capacitor placed on each pin, with an
additional 4.7µF to 22µF capacitor placed on the PLL supply pin (VDDPLL). 0.01µF capacitors are typically
recommended for each pin. Additional filtering including ferrite beads may be necessary for noisy systems. It is
recommended to place a 0 resistor at the bypass capacitors that connect to each power pin to allow for
additional filtering if needed. A large bulk capacitor is recommended at the point of power entry. This is typically
in the 50µF to 100µF range.
Layout Guidelines
Circuit board layout and stack-up for the LVDS serializer devices should be designed to provide low-noise power
feed to the device. Good layout practice will also separate high frequency or high-level inputs and outputs to
minimize unwanted stray noise pickup, feedback and interference. Power system performance may be greatly
improved by using thin dielectrics (2 to 4 mils) for power / ground sandwiches. This arrangement provides plane
capacitance for the PCB power system with low-inductance parasitics, which has proven especially effective at
high frequencies, and makes the value and placement of external bypass capacitors less critical. This practice is
easier to implement in dense pcbs with many layers and may not be practical in simpler boards. External bypass
capacitors should include both RF ceramic and tantalum electrolytic types. RF capacitors may use values in the
range of 0.01 uF to 0.1 uF. Tantalum capacitors may be in the 2.2 uF to 10 uF range. Voltage rating of the
tantalum capacitors should be at least 5X the power supply voltage being used.
Surface mount capacitors are recommended due to their smaller parasitics. When using multiple capacitors per
supply pin, locate the smaller value closer to the pin. It is recommended to connect power and ground pins
directly to the power and ground planes with bypass capacitors connected to the plane with vias on both ends of
the capacitor.
Copyright © 2012–2013, Texas Instruments Incorporated
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