DS90C185_13 Datasheet, PDF (3/22 Pages) Texas Instruments – Low Power 1.8V FPD-Link (LVDS) Serializer

DS90C185
www.ti.com
SNLS402D – FEBRUARY 2012 – REVISED FEBRUARY 2013
Pin Name
I/O
No.
1.8 V LVCMOS VIDEO INPUTS
D27-D21,
D20,
D19-D14,
D13-D9,
D8-D1,
D0
I
22-16,
14,
12-7,
5-1,
47-40,
38
CLK
I
6
LVDS VIDEO OUTPUTS
TxOUT0 –/+,
TxOUT1 –/+,
TxOUT2 –/+,
TxOUT3 –/+,
O
36, 35
34, 33
32, 31
28, 27
TxCLK OUT -/+
O
30, 29
1.8 V LVCMOS CONTROL INPUTS
R_FB
I
23
18B_Mode
I
26
VOD_SEL
I
39
PDB
I
37
POWER and GROUND
VDD
P
VDDTX
P
VDDPLL
P
GND
G
DAP
G
48
25
13
15, 24
Table 1. DS90C185 Pin Descriptions
Description
Data input pins.
This includes: 8 Red, 8 Green, 8 Blue, and 3 video control lines and a general purpose or L/R
control bit. Includes pull down.
Clock input.
Includes pull down.
LVDS Output Data — Expects 100 Ω DC load.
LVDS Output Clock — Expects 100 Ω DC load.
LVCMOS Ievel programmable strobe select
1 = Rising Edge Clock
0 = Falling Edge Clock — default
Includes pull down.
Mode Configuration Input
1 = 3D+C (18 bit RGB mode)
0 = 4D+C (24 bit RGB mode) — default
Includes pull down.
VOD Select Input
0 = Reduced V_OD (lower power)
1 = Normal V_OD — default
Includes pull down.
Power Down Bar(Sleep) Input
1 = ACTIVE
0 = Sleep State (low power idle) — default
Includes pull down.
Digital power input
LVDS driver power input
PLL power input
Ground pins
Connect DAP to ground plane
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
Copyright © 2012–2013, Texas Instruments Incorporated
Product Folder Links: DS90C185
Submit Documentation Feedback
3