DS90C185_13 Datasheet, PDF (7/22 Pages) Texas Instruments – Low Power 1.8V FPD-Link (LVDS) Serializer

DS90C185
www.ti.com
SNLS402D – FEBRUARY 2012 – REVISED FEBRUARY 2013
Recommended Transmitter Input Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified
Symbol
Parameter
Min
Typ
TCIT
TxCLK IN Transition Time (Figure 5)
1.0
TCIP
TxCLK IN Period (Figure 6)
9.52
T
TCIH
TxCLK IN High Time (Figure 6)
0.35T
0.5T
TCIL
TxCLK IN Low Time (Figure 6)
0.35T
0.5T
Max
6.0
40
0.65T
0.65T
Units
ns
ns
ns
ns
Transmitter Switching Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified
Symbol
Parameter
Min
LLHT
LVDS Low-to-High Transition Time (Figure 4 ⁽¹⁾)
LHLT
LVDS High-to-Low Transition Time (Figure 4 ⁽¹⁾)
TPPOS0
Transmitter Output Pulse Positions Normalized for Bit f = 105 MHz
0
Figure 10
TPPOS1
Transmitter Output Pulse Positions Normalized for Bit
1
TPPOS2
Transmitter Output Pulse Positions Normalized for Bit
2
TPPOS3
Transmitter Output Pulse Positions Normalized for Bit
3
TPPOS4
Transmitter Output Pulse Positions Normalized for Bit
4
TPPOS5
Transmitter Output Pulse Positions Normalized for Bit
5
TPPOS6
Transmitter Output Pulse Positions Normalized for Bit
6
ΔTPPOS Variation in Transmitter Pulse Position (Bit 6 — Bit 0)
TSTC
Required TxIN Setup to TxCLK IN
Figure 6
0
THTC
TCCJ
Required TxIN Hold to TxCLK IN
Cycle to Cycle Jitter
2.5
f = 105 MHz⁽¹⁾
TSD
Serializer Propagation Delay
f = 105 MHz
Figure 7
TCCS
TxOUT Channel to Channel Skew
TPLLS
TPPD
Transmitter Phase Lock Loop Set
Transmitter Power Down Delay
Figure 8
Figure 9⁽²⁾
(1) Parameter is guaranteed by characterization and is not tested at final test.
(2) Parameter is guaranteed by design and is not tested at final test.
Typ
0.18
0.18
1
2
3
4
5
6
7
±0.06
0.028
2*TCIP +
10.54
110
Max
0.5
0.5
0.035
2*TCIP +
13.96
1
100
Units
ns
ns
UI
UI
UI
UI
UI
UI
UI
UI
ns
ns
UI
ns
ps
ms
ns
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