DS90C185_13 Datasheet, PDF (13/22 Pages) Texas Instruments – Low Power 1.8V FPD-Link (LVDS) Serializer

DS90C185
www.ti.com
SNLS402D – FEBRUARY 2012 – REVISED FEBRUARY 2013
Table 3. 24bpp / LSB on CH3 (continued)
DS90C187 Input
D20
D19
D18
D27
Color Mapping
DE
VS
HS
GP
Note
Data Enable
Vertical Sync
Horizontal Sync
General Purpose
DS90C187 Input
D5
D4
D3
D2
D1
D0
D11
D10
D9
D8
D7
D6
D17
D16
D15
D14
D13
D12
D20
D19
D18
Table 4. 18bpp
Color Mapping
R5
R4
R3
R2
R1
R0
G5
G4
G3
G2
G1
G0
B5
B4
B3
B2
B1
B0
DE
VS
HS
Note
MSB
LSB
MSB
LSB
MSB
Data Enable
Vertical Sync
Horizontal Sync
FUNCTIONAL DESCRIPTION
DS90C185 converts a wide parallel LVCMOS input bus into FPD-Link LVDS data. The device can be configured
to support RGB-888 (24 bit color) or RGB-666 (18 bit color). The DS90C185 has several power saving features
including: selectable VOD, 18 bit / 24 bit mode select, and a power down pin control.
In each input pixel clock cycle, data from D[27:0] is serialized and driven out on TxOUT[3:0] +/- with TxCLKOUT
+/-. If 18B_MODE is LOW, then TxOUT3 +/- is powered down and the corresponding LVCMOS input signals are
ignored.
The input pixel clock can range from 25 MHz to 105 MHz, resulting in a total maximum payload of 700 Mbps (28
bits * 25MHz) to 2.94 Gbps (28 bits * 105 MHz). Each LVDS driver will operate at a speed of 7 bits per input
clock cycle, resulting in a serial line rate of 175 Mbps to 735 Mbps. TxCLKOUT +/- will operate at the same rate
as CLK with a duty cycle ratio of 57:43.
Pixel Clock Edge Select (RFB)
The RFB pin determines the edge that the input LVCMOS data is latched on. If RFB is HIGH, input data is
latched on the RISING EDGE of the pixel clock (CLK). If RFB is LOW, the input data is latched on the FALLING
EDGE of the pixel clock. Note: This can be set independently of receiver’s output clock strobe.
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