DS100BR111A Datasheet, PDF (8/35 Pages) Texas Instruments – Ultra Low Power 10.3 Gbps 2-Channel Repeaters with Input Equalization and Output De-Emphasis

Symbol
Parameter
Conditions
Min
T_CCSK
Inter-pair Channel
Skew
T = 25°C, VDD = 2.5V
T_PPSK
Part to Part Channel
Skew
T = 25°C, VDD = 2.5V
T_{TX-IDLE-SET-TO-}
IDLE
Max time to transition to VIN = 1Vpp, 10 Gbps
idle after differential EQ = 00, DE = 0
signal
T_{TX-IDLE-TO-DIFF-} Max time to transition to VIN = 1Vpp, 10 Gbps
DATA
valid differential signal EQ = 00, DE = 0
after idle
T_{ENVELOPE_DIST}
ORT
Active OOB timing
distortion, input active
time vs. output active
time
Typ
Max
7
20
6.5
3.2
3.3
Units
ps
ps
ns
ns
ns
Symbol
Parameter
Conditions
Min
OUTPUT JITTER SPECIFICATIONS (Note 4)
R_J
Random Jitter
No Media
D_J1
Deterministic Jitter ^{Source Amplitude = 700 mV,}
PRBS15 pattern,
10.3125 Gbps
VOD = 850 mV, EQ =
minimum, DE = 0 dB
Typ
Max
Units
0.3
ps (RMS)
0.09
UI
Equalization
D_JE1
Residual Deterministic 8 meter 30AWG Cable on
0.23
UI
Jitter
Inputs
10.3125 Gbps
Source = 700 mV, PRBS15
pattern
EQ = 2B'h
D_JE2
Residual Deterministic
30" FR4 on Inputs
0.15
UI
Jitter
Source = 700 mV, PRBS15
10.3125 Gbps
pattern
EQ = 17'h
De-emphasis
D_JD1
Residual Deterministic 10” 4 mil stripline FR4 on
0.14
UI
Jitter
Outputs
10.3125 Gbps
Source = 700 mV, PRBS15
pattern
EQ = Min, VOD = 1050, DE
= 010
Note 2: “Absolute Maximum Ratings” indicate limits beyond which damage
to the device may occur, including inoperability and degradation of device
reliability and/or performance. Functional operation of the device and/or non-
degradation at the Absolute Maximum Ratings or other conditions beyond
those indicated in the Recommended Operating Conditions is not implied.
The Recommended Operating Conditions indicate conditions at which the
device is functional and the device should not be operated beyond such
conditions. Absolute Maximum Numbers are guaranteed for a junction
temperature range of -40°C to +125°C. Models are validated to Maximum
Operating Voltages only.
Note 3: Input is held to a maximum of 50 mV below VDD or VIN to simulate
the use of a 1K resistor on the input.
Note 4: Typical jitter reported is determined by jitter decomposition software
on the DSA8200 Oscilloscope.
Note 5: VOH only applies to the DONE# pin; LOS, SCL, and SDA are open-
drain outputs that have no internal pull-up capability. DONE# is a full
LVCMOS output with pull-up and pull-down capability
Note 6: Force +/- 100 uA on output, measure delta V on the Output and
calculate impedance. Mismatch is the percentage difference of OUTn+ and
OUTn- impedance driving the same logic state.
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