DS100BR111A Datasheet, PDF (15/35 Pages) Texas Instruments – Ultra Low Power 10.3 Gbps 2-Channel Repeaters with Input Equalization and Output De-Emphasis

System Management Bus (SMBus) and Configuration
Registers
The System Management Bus interface is compatible to SM-
Bus 2.0 physical layer specification. ENSMB must be pulled
high to enable SMBus mode and allow access to the config-
uration registers.
The DS100BR111A has AD[3:0] inputs in SMBus mode.
These pins are the user set SMBus slave address inputs.
When pulled low the AD[3:0] = 0000'b, the device default ad-
dress byte is B0'h. Based on the SMBus 2.0 specification, this
configuration results in a 7-bit slave address of 1011000'b.
The LSB is set to 0'b (for a WRITE), thus the 8-bit value is
1011 0000'b or B0'h. The device address byte can be set with
the use of the AD[3:0] inputs.
Shown in the form of an expression:
Slave Address [7:4] = The DS100BR111A hardware address
(1011'b) + Address pin AD[3]
Slave Address [3:1] = Address pins AD[2:0]
Slave Address [0] = 0'b for a WRITE or 1'b for a READ
Slave Address Examples:
• AD[3:0] = 0001'b, the device slave address byte is B2'h
— Slave Address [7:4] = 1011'b + 0'b = 1011'b or B'h
— Slave Address [3:1] = 001'b
— Slave Address [0] = 0'b for a WRITE
• AD[3:0] = 0010'b, the device slave address byte is B4'h
— Slave Address [7:4] = 1011'b + 0'b = 1011'b or B'h
— Slave Address [3:1] = 010'b
— Slave Address [0] = 0'b for a WRITE
• AD[3:0] = 0100'b, the device slave address byte is B8'h
— Slave Address [7:4] = 1011'b + 0'b = 1011'b or B'h
— Slave Address [3:1] = 100'b
— Slave Address [0] = 0'b for a WRITE
• AD[3:0] = 1000'b, the device slave address byte is C0'h
— Slave Address [7:4] = 1011'b + 1'b = 1100'b or C'h
— Slave Address [3:1] = 000'b
— Slave Address [0] = 0'b for a WRITE
TRANSFER OF DATA VIA THE SMBus
During normal operation the data on SDA must be stable dur-
ing the time when SCL is High.
There are three unique states for the SMBus:
START: A High-to-Low transition on SDA while SCL is High
indicates a message START condition.
STOP: A Low-to-High transition on SDA while SCL is High
indicates a message STOP condition.
IDLE: If SCL and SDA are both High for a time exceeding
t_BUF from the last detected STOP condition or if they are High
for a total exceeding the maximum specification for t_HIGH then
the bus will transfer to the IDLE state.
SMBus TRANSACTIONS
The device supports WRITE and READ transactions. See
Register Description table for register address, type (Read/
Write, Read Only), default value and function information.
WRITING A REGISTER
To write a register, the following protocol is used (see SMBus
2.0 specification).
1. The Host drives a START condition, the 7-bit SMBus
address, and a “0” indicating a WRITE.
2. The Device (Slave) drives the ACK bit (“0”).
3. The Host drives the 8-bit Register Address.
4. The Device drives an ACK bit (“0”).
5. The Host drive the 8-bit data byte.
6. The Device drives an ACK bit (“0”).
7. The Host drives a STOP condition.
The WRITE transaction is completed, the bus goes IDLE and
communication with other SMBus devices may now occur.
READING A REGISTER
To read a register, the following protocol is used (see SMBus
2.0 specification).
1. The Host drives a START condition, the 7-bit SMBus
address, and a “0” indicating a WRITE.
2. The Device (Slave) drives the ACK bit (“0”).
3. The Host drives the 8-bit Register Address.
4. The Device drives an ACK bit (“0”).
5. The Host drives a START condition.
6. The Host drives the 7-bit SMBus Address, and a “1”
indicating a READ.
7. The Device drives an ACK bit “0”.
8. The Device drives the 8-bit data value (register contents).
9. The Host drives a NACK bit “1”indicating end of the
READ transfer.
10. The Host drives a STOP condition.
The READ transaction is completed, the bus goes IDLE and
communication with other SMBus devices may now occur.
Please see SMBus Register Map Table for more information.
FIGURE 5. Typical SMBus Write Operation
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